Copyright (C) 1995-2018 FinalWire Ltd. All rights reserved. aida_bench64.dll build: 4.3.790.0 Oct 17 2018 09:21:32 J1900N Arch:X64 CPUCount:4 NUMA:0 Freq: 1999.92MHz Priority:080 OS:6.3.17134 Memory: 8281484KB AllocGran:0x00010000 P:0x00001000 LP:0x0000000000200000 Memory To Test:16384KB 4K DTLB:128 2M DTLB: 16 CLFlush:64 ProcMask: 0x000000000000000f Features: X86,TSC,X87,CMOV,MMX,SSE,SSE2,SSE3,AMD64,SSSE3,SSE4.1,SSE4.2,POPCNT,LAHF,CMPX8,CMPX16,CLMUL,MOVBE,RDRAND,CLFLUSH,TSCINV,RDTSCP,3DNOWPREF,LNOP,ERMS,PSE, CPU#000 Vendor: GenuineIntel Family: 6 Model: 37 Stepping: 3 CoreType:0x20030673 CPU#000 Type: " Intel(R) Celeron(R) CPU J1900 @ 1.99GHz" CPU#000 AffMask: 0x0000000000000001 CPU#000 PhysMask:0x000000000000000f CPU#000 APIC_ID:0x00000000 Phys_ID:000 Core_ID:00 SMT_ID:00 CPU#000 L1I cache: 32KB, 64 byte cache line, 8 way, SMask:0000000000000001 CPU#000 L1D cache: 24KB, 64 byte cache line, 6 way, SMask:0000000000000001 CPU#000 L2 cache: 1024KB, 64 byte cache line, 16 way, SMask:0000000000000003, non-inclusive CPU#000 L0D 4K TLB: 32 entries, full, SMask:0000000000000001 CPU#000 L1D 4K TLB: 128 entries, 4 way, SMask:0000000000000001 CPU#000 L1D 2M TLB: 16 entries, 4 way, SMask:0000000000000001 CPU#000 L1I 4K TLB: 48 entries, full, SMask:0000000000000001 CPU#001 Vendor: GenuineIntel Family: 6 Model: 37 Stepping: 3 CoreType:0x20030673 CPU#001 Type: " Intel(R) Celeron(R) CPU J1900 @ 1.99GHz" CPU#001 AffMask: 0x0000000000000002 CPU#001 PhysMask:0x000000000000000f CPU#001 APIC_ID:0x00000002 Phys_ID:000 Core_ID:01 SMT_ID:00 CPU#001 L1I cache: 32KB, 64 byte cache line, 8 way, SMask:0000000000000002 CPU#001 L1D cache: 24KB, 64 byte cache line, 6 way, SMask:0000000000000002 CPU#001 L2 cache: 1024KB, 64 byte cache line, 16 way, SMask:0000000000000003, non-inclusive CPU#001 L0D 4K TLB: 32 entries, full, SMask:0000000000000002 CPU#001 L1D 4K TLB: 128 entries, 4 way, SMask:0000000000000002 CPU#001 L1D 2M TLB: 16 entries, 4 way, SMask:0000000000000002 CPU#001 L1I 4K TLB: 48 entries, full, SMask:0000000000000002 CPU#002 Vendor: GenuineIntel Family: 6 Model: 37 Stepping: 3 CoreType:0x20030673 CPU#002 Type: " Intel(R) Celeron(R) CPU J1900 @ 1.99GHz" CPU#002 AffMask: 0x0000000000000004 CPU#002 PhysMask:0x000000000000000f CPU#002 APIC_ID:0x00000004 Phys_ID:000 Core_ID:02 SMT_ID:00 CPU#002 L1I cache: 32KB, 64 byte cache line, 8 way, SMask:0000000000000004 CPU#002 L1D cache: 24KB, 64 byte cache line, 6 way, SMask:0000000000000004 CPU#002 L2 cache: 1024KB, 64 byte cache line, 16 way, SMask:000000000000000c, non-inclusive CPU#002 L0D 4K TLB: 32 entries, full, SMask:0000000000000004 CPU#002 L1D 4K TLB: 128 entries, 4 way, SMask:0000000000000004 CPU#002 L1D 2M TLB: 16 entries, 4 way, SMask:0000000000000004 CPU#002 L1I 4K TLB: 48 entries, full, SMask:0000000000000004 CPU#003 Vendor: GenuineIntel Family: 6 Model: 37 Stepping: 3 CoreType:0x20030673 CPU#003 Type: " Intel(R) Celeron(R) CPU J1900 @ 1.99GHz" CPU#003 AffMask: 0x0000000000000008 CPU#003 PhysMask:0x000000000000000f CPU#003 APIC_ID:0x00000006 Phys_ID:000 Core_ID:03 SMT_ID:00 CPU#003 L1I cache: 32KB, 64 byte cache line, 8 way, SMask:0000000000000008 CPU#003 L1D cache: 24KB, 64 byte cache line, 6 way, SMask:0000000000000008 CPU#003 L2 cache: 1024KB, 64 byte cache line, 16 way, SMask:000000000000000c, non-inclusive CPU#003 L0D 4K TLB: 32 entries, full, SMask:0000000000000008 CPU#003 L1D 4K TLB: 128 entries, 4 way, SMask:0000000000000008 CPU#003 L1D 2M TLB: 16 entries, 4 way, SMask:0000000000000008 CPU#003 L1I 4K TLB: 48 entries, full, SMask:0000000000000008 Instruction Latency: Used CPUs: 1 ProcMask: 0x0000000000000008 0 X86 :NOP L: [no true dep.] T: 0.25ns= 0.50c 1 X86 :0x66 NOP L: [no true dep.] T: 0.25ns= 0.50c 2 X86 : 2x 0x66 NOP L: [no true dep.] T: 0.25ns= 0.50c 3 X86 : 3x 0x66 NOP L: [no true dep.] T: 0.25ns= 0.50c 4 X86 : 4x 0x66 NOP L: [no true dep.] T: 3.00ns= 6.00c 5 X86 : 5x 0x66 NOP L: [no true dep.] T: 3.00ns= 6.00c 6 X86 : 6x 0x66 NOP L: [no true dep.] T: 3.00ns= 6.00c 7 X86 : 7x 0x66 NOP L: [no true dep.] T: 4.50ns= 9.00c 8 X86 : 8x 0x66 NOP L: [no true dep.] T: 3.50ns= 7.00c 9 X86 : 9x 0x66 NOP L: [no true dep.] T: 3.50ns= 7.00c 10 X86 :10x 0x66 NOP L: [no true dep.] T: 5.00ns= 10.00c 11 X86 :11x 0x66 NOP L: [no true dep.] T: 5.00ns= 10.00c 12 X86 :12x 0x66 NOP L: [no true dep.] T: 5.00ns= 10.00c 13 X86 :13x 0x66 NOP L: [no true dep.] T: 6.50ns= 13.00c 14 X86 :14x 0x66 NOP L: [no true dep.] T: 6.54ns= 13.08c 15 SSE2 :PAUSE L: [no true dep.] T: 12.00ns= 24.00c 16 X86 :MOV r8, imm8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 17 X86 :MOV r16, imm16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 18 X86 :MOV r32, imm32 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 19 AMD64 :MOV r64, imm64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 20 X86 :MOV r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 21 X86 :MOV r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 22 X86 :MOV r32, r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 23 AMD64 :MOV r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 24 X86 :MOV r8, [m8] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 25 X86 :MOV r16, [m16] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 26 X86 :MOV r32, [m32] L: 1.50ns= 3.0c T: 0.50ns= 1.00c 27 AMD64 :MOV r64, [m64] L: 1.50ns= 3.0c T: 0.50ns= 1.00c 28 X86 :MOV [m8], r8 L: [memory dep.] T: 0.50ns= 1.00c 29 X86 :MOV [m16], r16 L: [memory dep.] T: 0.50ns= 1.00c 30 X86 :MOV [m32], r32 L: [memory dep.] T: 0.50ns= 1.00c 31 X86 :MOV [m32 + 8], r32 L: [memory dep.] T: 0.50ns= 1.00c 32 AMD64 :MOV [m64], r64 L: [memory dep.] T: 0.50ns= 1.00c 33 AMD64 :MOV [m64 + 16], r64 L: [memory dep.] T: 0.50ns= 1.00c 34 X86 :MOV r8,[m8]+MOV [m8],r8 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 35 X86 :MOV r16,[m16]+MOV [m16],r16 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 36 X86 :MOV r32,[m32]+MOV [m32],r32 L: 2.00ns= 4.0c T: 1.00ns= 2.00c 37 AMD64 :MOV r64,[m64]+MOV [m64],r64 L: 2.00ns= 4.0c T: 1.00ns= 2.00c 38 SSE2 :MOVNTI [m32], r32 L: [memory dep.] T: 1.00ns= 1.00c 39 AMD64 :MOVNTI [m64], r64 L: [memory dep.] T: 1.00ns= 1.00c 40 CMOV :CMOVNZ r16, r16 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 41 CMOV :CMOVNZ r32, r32 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 42 AMD64 :CMOVNZ r64, r64 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 43 X86 :MOVSX r16, r8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 44 X86 :MOVSX r32, r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 45 AMD64 :MOVSX r64, r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 46 X86 :MOVSX r32, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 47 AMD64 :MOVSX r64, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 48 AMD64 :MOVSXD r64, r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 49 X86 :MOVZX r16, r8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 50 X86 :MOVZX r32, r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 51 AMD64 :MOVZX r64, r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 52 X86 :MOVZX r32, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 53 AMD64 :MOVZX r64, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 54 X86 :XCHG r8, r8 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 55 X86 :XCHG r16, r16 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 56 X86 :XCHG r32, r32 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 57 AMD64 :XCHG r64, r64 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 58 X86 :XCHG r1_8, r2_8 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 59 X86 :XCHG r1_16, r2_16 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 60 X86 :XCHG r1_32, r2_32 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 61 AMD64 :XCHG r1_64, r2_64 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 62 X86 :XCHG r8, [m8] L: 5.00ns= 10.0c T: 5.17ns= 10.33c 63 X86 :XCHG r16, [m16] L: 5.00ns= 10.0c T: 5.17ns= 10.33c 64 X86 :XCHG r32, [m32] L: 5.00ns= 10.0c T: 5.17ns= 10.33c 65 AMD64 :XCHG r64, [m64] L: 5.00ns= 10.0c T: 5.21ns= 10.42c 66 X86 :ADD r32, 0x04000 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 67 X86 :ADD r32, 0x08000 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 68 X86 :ADD r32, 0x10000 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 69 X86 :ADD r32, 0x20000 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 70 X86 :ADD r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 71 X86 :ADD r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 72 X86 :ADD r32, r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 73 AMD64 :ADD r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 74 X86 :ADD r8, [m8] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 75 X86 :ADD r16, [m16] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 76 X86 :ADD r32, [m32] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 77 AMD64 :ADD r64, [m64] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 78 X86 :ADD [m8], r8 L: 3.00ns= 6.0c T: 0.50ns= 1.00c 79 X86 :ADD [m16], r16 L: 3.00ns= 6.0c T: 0.54ns= 1.08c 80 X86 :ADD [m32], r32 L: 3.00ns= 6.0c T: 0.50ns= 1.00c 81 X86 :ADD [m32 + 8], r32 L: 3.00ns= 6.0c T: 0.50ns= 1.00c 82 AMD64 :ADD [m64], r64 L: 2.92ns= 5.8c T: 0.50ns= 1.00c 83 AMD64 :ADD [m64 + 16], r64 L: 3.00ns= 6.0c T: 0.50ns= 1.00c 84 X86 :LOCK ADD [m8], r8 L: 5.21ns= 10.4c T: 5.21ns= 10.42c 85 X86 :LOCK ADD [m16], r16 L: 5.21ns= 10.4c T: 5.25ns= 10.50c 86 X86 :LOCK ADD [m32], r32 L: 5.21ns= 10.4c T: 5.25ns= 10.50c 87 X86 :LOCK ADD [m32 + 8], r32 L: 5.25ns= 10.5c T: 5.25ns= 10.50c 88 AMD64 :LOCK ADD [m64], r64 L: 5.21ns= 10.4c T: 5.25ns= 10.50c 89 AMD64 :LOCK ADD [m64 + 16], r64 L: 5.21ns= 10.4c T: 5.38ns= 10.75c 90 X86 :ADD r8, imm8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 91 X86 :ADD r16, imm8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 92 X86 :ADD r32, imm8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 93 AMD64 :ADD r64, imm8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 94 X86 :ADD r16, imm16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 95 X86 :ADD r32, imm32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 96 AMD64 :ADD r64, imm32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 97 X86 :ADD [m8], imm8 L: 3.00ns= 6.0c T: 0.50ns= 1.00c 98 X86 :ADD [m16], imm8 L: 2.71ns= 5.4c T: 0.50ns= 1.00c 99 X86 :ADD [m32], imm8 L: 2.75ns= 5.5c T: 0.50ns= 1.00c 100 AMD64 :ADD [m64], imm8 L: 2.83ns= 5.7c T: 0.50ns= 1.00c 101 X86 :ADD [m16], imm16 L: 2.96ns= 5.9c T: 0.50ns= 1.00c 102 X86 :ADD [m32], imm32 L: 2.67ns= 5.3c T: 0.50ns= 1.00c 103 AMD64 :ADD [m64], imm32 L: 2.83ns= 5.7c T: 0.50ns= 1.00c 104 X86 :ADD al, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 105 X86 :ADD ax, imm16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 106 X86 :ADD eax, imm32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 107 AMD64 :ADD rax, imm32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 108 X86 :SUB r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 109 X86 :SUB r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 110 X86 :SUB r32, r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 111 AMD64 :SUB r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 112 X86 :SUB r1_8, r2_8 L: 0.50ns= 1.0c T: 0.24ns= 0.47c 113 X86 :SUB r1_16, r2_16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 114 X86 :SUB r1_32, r2_32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 115 AMD64 :SUB r1_64, r2_64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 116 X86 :ADC r8, r8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 117 X86 :ADC r16, r16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 118 X86 :ADC r32, r32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 119 AMD64 :ADC r64, r64 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 120 X86 :SBB r8, r8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 121 X86 :SBB r16, r16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 122 X86 :SBB r32, r32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 123 AMD64 :SBB r64, r64 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 124 X86 :SBB r1_8, r2_8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 125 X86 :SBB r1_16, r2_16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 126 X86 :SBB r1_32, r2_32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 127 AMD64 :SBB r1_64, r2_64 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 128 X86 :CMP r8, r8 L: [no true dep.] T: 0.25ns= 0.50c 129 X86 :CMP r16, r16 L: [no true dep.] T: 0.25ns= 0.50c 130 X86 :CMP r32, r32 L: [no true dep.] T: 0.25ns= 0.50c 131 AMD64 :CMP r64, r64 L: [no true dep.] T: 0.25ns= 0.50c 132 X86 :CMP r1_8, r2_8 L: [no true dep.] T: 0.25ns= 0.50c 133 X86 :CMP r1_16, r2_16 L: [no true dep.] T: 0.25ns= 0.50c 134 X86 :CMP r1_32, r2_32 L: [no true dep.] T: 0.25ns= 0.50c 135 AMD64 :CMP r1_64, r2_64 L: [no true dep.] T: 0.25ns= 0.50c 136 X86 :AND r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 137 X86 :AND r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 138 X86 :AND r32, r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 139 AMD64 :AND r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 140 X86 :AND r1_8, r2_8 L: 0.50ns= 1.0c T: 0.24ns= 0.47c 141 X86 :AND r1_16, r2_16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 142 X86 :AND r1_32, r2_32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 143 AMD64 :AND r1_64, r2_64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 144 X86 :OR r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 145 X86 :OR r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 146 X86 :OR r32, r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 147 AMD64 :OR r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 148 X86 :OR r1_8, r2_8 L: 0.50ns= 1.0c T: 0.24ns= 0.47c 149 X86 :OR r1_16, r2_16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 150 X86 :OR r1_32, r2_32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 151 AMD64 :OR r1_64, r2_64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 152 X86 :XOR r8, r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 153 X86 :XOR r16, r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 154 X86 :XOR r32, r32 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 155 AMD64 :XOR r64, r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 156 X86 :XOR r1_8, r2_8 L: 0.50ns= 1.0c T: 0.24ns= 0.47c 157 X86 :XOR r1_16, r2_16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 158 X86 :XOR r1_32, r2_32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 159 AMD64 :XOR r1_64, r2_64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 160 X86 :NEG r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 161 X86 :NEG r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 162 X86 :NEG r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 163 AMD64 :NEG r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 164 X86 :NOT r8 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 165 X86 :NOT r16 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 166 X86 :NOT r32 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 167 AMD64 :NOT r64 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 168 X86 :TEST r8, r8 L: [no true dep.] T: 0.25ns= 0.50c 169 X86 :TEST r16, r16 L: [no true dep.] T: 0.25ns= 0.50c 170 X86 :TEST r32, r32 L: [no true dep.] T: 0.25ns= 0.50c 171 AMD64 :TEST r64, r64 L: [no true dep.] T: 0.25ns= 0.50c 172 X86 :TEST r1_8, r2_8 L: [no true dep.] T: 0.25ns= 0.50c 173 X86 :TEST r1_16, r2_16 L: [no true dep.] T: 0.25ns= 0.50c 174 X86 :TEST r1_32, r2_32 L: [no true dep.] T: 0.25ns= 0.50c 175 AMD64 :TEST r1_64, r2_64 L: [no true dep.] T: 0.25ns= 0.50c 176 X86 :BT r16, r16 L: [no true dep.] T: 0.50ns= 1.00c 177 X86 :BT r32, r32 L: [no true dep.] T: 0.50ns= 1.00c 178 AMD64 :BT r64, r64 L: [no true dep.] T: 0.50ns= 1.00c 179 X86 :BT r16, imm8 L: [no true dep.] T: 0.50ns= 1.00c 180 X86 :BT r32, imm8 L: [no true dep.] T: 0.50ns= 1.00c 181 AMD64 :BT r64, imm8 L: [no true dep.] T: 0.50ns= 1.00c 182 X86 :BTC r16, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 183 X86 :BTC r32, r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 184 AMD64 :BTC r64, r64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 185 X86 :BTC r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 186 X86 :BTC r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 187 AMD64 :BTC r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 188 X86 :BTR r16, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 189 X86 :BTR r32, r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 190 AMD64 :BTR r64, r64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 191 X86 :BTR r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 192 X86 :BTR r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 193 AMD64 :BTR r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 194 X86 :BTS r16, r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 195 X86 :BTS r32, r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 196 AMD64 :BTS r64, r64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 197 X86 :BTS r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 198 X86 :BTS r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 199 AMD64 :BTS r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 200 X86 :SETC r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 201 X86 :INC r8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 202 X86 :INC r16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 203 X86 :INC r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 204 AMD64 :INC r64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 205 AMD64 :LEA r16, [r64 + r64] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 206 AMD64 :LEA r32, [r64 + r64] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 207 AMD64 :LEA r64, [r64 + r64] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 208 AMD64 :LEA r16, [r64 + r64 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 209 AMD64 :LEA r32, [r64 + r64 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 210 AMD64 :LEA r64, [r64 + r64 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 211 AMD64 :LEA r16, [r64 + r64 * 8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 212 AMD64 :LEA r32, [r64 + r64 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 213 AMD64 :LEA r64, [r64 + r64 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 214 AMD64 :LEA r16, [r64 + r64 * 8 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 215 AMD64 :LEA r32, [r64 + r64 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 216 AMD64 :LEA r64, [r64 + r64 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 217 X86 :SHL r8, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 218 X86 :SHL r16, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 219 X86 :SHL r32, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 220 AMD64 :SHL r64, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 221 X86 :SHL r8, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 222 X86 :SHL r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 223 X86 :SHL r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 224 AMD64 :SHL r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 225 X86 :SHL r8, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 226 X86 :SHL r16, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 227 X86 :SHL r32, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 228 AMD64 :SHL r64, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 229 X86 :SHR r8, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 230 X86 :SHR r16, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 231 X86 :SHR r32, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 232 AMD64 :SHR r64, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 233 X86 :SHR r8, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 234 X86 :SHR r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 235 X86 :SHR r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 236 AMD64 :SHR r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 237 X86 :SHR r8, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 238 X86 :SHR r16, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 239 X86 :SHR r32, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 240 AMD64 :SHR r64, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 241 X86 :SAR r8, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 242 X86 :SAR r16, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 243 X86 :SAR r32, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 244 AMD64 :SAR r64, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 245 X86 :SAR r8, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 246 X86 :SAR r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 247 X86 :SAR r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 248 AMD64 :SAR r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 249 X86 :SAR r8, cl L: 0.50ns= 1.0c T: 0.46ns= 0.92c 250 X86 :SAR r16, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 251 X86 :SAR r32, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 252 AMD64 :SAR r64, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 253 X86 :SHLD r1_16, r1_16, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 254 X86 :SHLD r1_32, r1_32, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 255 AMD64 :SHLD r1_64, r1_64, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 256 X86 :SHLD r1_16, r1_16, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 257 X86 :SHLD r1_32, r1_32, cl L: 2.00ns= 4.0c T: 2.00ns= 4.00c 258 AMD64 :SHLD r1_64, r1_64, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 259 X86 :SHRD r1_16, r1_16, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 260 X86 :SHRD r1_32, r1_32, imm8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 261 AMD64 :SHRD r1_64, r1_64, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 262 X86 :SHRD r1_16, r1_16, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 263 X86 :SHRD r1_32, r1_32, cl L: 2.00ns= 4.0c T: 2.00ns= 4.00c 264 AMD64 :SHRD r1_64, r1_64, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 265 X86 :ROL r8, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 266 X86 :ROL r16, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 267 X86 :ROL r32, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 268 AMD64 :ROL r64, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 269 X86 :ROL r8, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 270 X86 :ROL r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 271 X86 :ROL r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 272 AMD64 :ROL r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 273 X86 :ROL r8, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 274 X86 :ROL r16, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 275 X86 :ROL r32, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 276 AMD64 :ROL r64, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 277 X86 :ROR r8, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 278 X86 :ROR r16, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 279 X86 :ROR r32, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 280 AMD64 :ROR r64, 1 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 281 X86 :ROR r8, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 282 X86 :ROR r16, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 283 X86 :ROR r32, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 284 AMD64 :ROR r64, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 285 X86 :ROR r8, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 286 X86 :ROR r16, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 287 X86 :ROR r32, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 288 AMD64 :ROR r64, cl L: 0.50ns= 1.0c T: 0.50ns= 1.00c 289 X86 :RCL r8, 1 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 290 X86 :RCL r16, 1 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 291 X86 :RCL r32, 1 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 292 AMD64 :RCL r64, 1 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 293 X86 :RCL r8, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 294 X86 :RCL r16, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 295 X86 :RCL r32, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 296 AMD64 :RCL r64, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 297 X86 :RCL r8, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 298 X86 :RCL r16, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 299 X86 :RCL r32, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 300 AMD64 :RCL r64, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 301 X86 :RCR r8, 1 L: 4.50ns= 9.0c T: 4.50ns= 9.00c 302 X86 :RCR r16, 1 L: 4.50ns= 9.0c T: 4.50ns= 9.00c 303 X86 :RCR r32, 1 L: 4.50ns= 9.0c T: 4.50ns= 9.00c 304 AMD64 :RCR r64, 1 L: 4.50ns= 9.0c T: 4.50ns= 9.00c 305 X86 :RCR r8, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 306 X86 :RCR r16, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 307 X86 :RCR r32, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 308 AMD64 :RCR r64, imm8 L: 6.00ns= 12.0c T: 6.00ns= 12.00c 309 X86 :RCR r8, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 310 X86 :RCR r16, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 311 X86 :RCR r32, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 312 AMD64 :RCR r64, cl L: 6.00ns= 12.0c T: 6.00ns= 12.00c 313 X86 :BSF r16, r16 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 314 X86 :BSF r32, r32 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 315 AMD64 :BSF r64, r64 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 316 X86 :BSR r16, r16 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 317 X86 :BSR r32, r32 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 318 AMD64 :BSR r64, r64 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 319 X86 :BSWAP r32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 320 AMD64 :BSWAP r64 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 321 MOVBE :MOVBE r16, [m16] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 322 MOVBE :MOVBE r32, [m32] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 323 MOVBE :MOVBE r64, [m64] L: 2.00ns= 4.0c T: 0.50ns= 1.00c 324 MOVBE :MOVBE [m16], r16 L: [memory dep.] T: 0.96ns= 1.92c 325 MOVBE :MOVBE [m32], r32 L: [memory dep.] T: 0.67ns= 1.33c 326 MOVBE :MOVBE [m64], r64 L: [memory dep.] T: 0.67ns= 1.33c 327 X86 :IMUL r16, r16 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 328 X86 :IMUL r32, r32 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 329 AMD64 :IMUL r64, r64 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 330 X86 :IMUL r16, r16, imm8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 331 X86 :IMUL r32, r32, imm8 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 332 AMD64 :IMUL r64, r64, imm8 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 333 X86 :IMUL r16, r16, imm16 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 334 X86 :IMUL r32, r32, imm32 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 335 AMD64 :IMUL r64, r64, imm32 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 336 X86 :IMUL r8 (ah) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 337 X86 :IMUL r16 (dx) L: 2.67ns= 5.3c T: 2.50ns= 5.00c 338 X86 :IMUL r32 (edx) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 339 AMD64 :IMUL r64 (rdx) L: 3.50ns= 7.0c T: 3.50ns= 7.00c 340 X86 :MUL r8 (ah) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 341 X86 :MUL r16 (dx) L: 2.63ns= 5.3c T: 2.50ns= 5.00c 342 X86 :MUL r32 (edx) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 343 AMD64 :MUL r64 (rdx) L: 3.50ns= 7.0c T: 3.50ns= 7.00c 344 X86 :IMUL r8 (al) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 345 X86 :IMUL r16 (ax) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 346 X86 :IMUL r32 (eax) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 347 AMD64 :IMUL r64 (rax) L: 3.50ns= 7.0c T: 3.50ns= 7.00c 348 X86 :MUL r8 (al) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 349 X86 :MUL r16 (ax) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 350 X86 :MUL r32 (eax) L: 2.50ns= 5.0c T: 2.50ns= 5.00c 351 AMD64 :MUL r64 (rax) L: 3.50ns= 7.0c T: 3.50ns= 7.00c 352 X86 :IDIV r8 14/ 7b (full) L: 16.50ns= 33.0c T: 16.50ns= 33.00c 353 X86 :IDIV r8 12/ 7b ax upd L: 17.75ns= 35.5c T: 17.38ns= 34.75c 354 X86 :IDIV r8 7/ 7b ax upd L: 17.75ns= 35.5c T: 17.38ns= 34.75c 355 X86 :IDIV r8 4/ 7b ax upd L: [no true dep.] T: 17.38ns= 34.75c 356 X86 :IDIV r8 0/ 7b L: [no true dep.] T: 16.67ns= 33.33c 357 X86 :IDIV r8 11/ 4b ax upd L: 17.75ns= 35.5c T: 17.38ns= 34.75c 358 X86 :IDIV r8 8/ 4b ax upd L: [no true dep.] T: 17.38ns= 34.75c 359 X86 :IDIV r8 4/ 4b ax upd L: 17.75ns= 35.5c T: 17.38ns= 34.75c 360 X86 :IDIV r8 0/ 4b L: [no true dep.] T: 16.67ns= 33.33c 361 X86 :IDIV r8 2^12/2^6 ax upd L: [no true dep.] T: 17.38ns= 34.75c 362 X86 :IDIV r8 1/1 L: 16.50ns= 33.0c T: 16.50ns= 33.00c 363 X86 :IDIV r8 1/1 ax upd L: 17.75ns= 35.5c T: 17.38ns= 34.75c 364 X86 :IDIV r16 30/15b (full) L: 19.33ns= 38.7c T: 18.25ns= 36.50c 365 X86 :IDIV r16 24/15b ax upd L: 20.29ns= 40.6c T: 19.75ns= 39.50c 366 X86 :IDIV r16 15/15b ax upd L: 18.29ns= 36.6c T: 17.75ns= 35.50c 367 X86 :IDIV r16 8/15b ax/dx upd L: [no true dep.] T: 19.00ns= 38.00c 368 X86 :IDIV r16 0/15b L: [no true dep.] T: 16.25ns= 32.50c 369 X86 :IDIV r16 23/ 8b ax upd L: 20.29ns= 40.6c T: 19.75ns= 39.50c 370 X86 :IDIV r16 16/ 8b ax upd L: [no true dep.] T: 19.75ns= 39.50c 371 X86 :IDIV r16 8/ 8b ax upd L: 18.29ns= 36.6c T: 17.75ns= 35.50c 372 X86 :IDIV r16 0/ 8b L: [no true dep.] T: 16.25ns= 32.50c 373 X86 :IDIV r16 2^28/2^14 ax/dx L: [no true dep.] T: 21.00ns= 42.00c 374 X86 :IDIV r16 1/1 L: 17.33ns= 34.7c T: 16.25ns= 32.50c 375 X86 :IDIV r16 1/1 ax upd L: 18.29ns= 36.6c T: 17.75ns= 35.50c 376 X86 :IDIV r16 1/1 ax/dx upd L: 17.79ns= 35.6c T: 17.79ns= 35.58c 377 X86 :IDIV r32 62/31b (full) L: 23.33ns= 46.7c T: 22.25ns= 44.50c 378 X86 :IDIV r32 62/31b 0 rem. L: 23.33ns= 46.7c T: 22.25ns= 44.50c 379 X86 :IDIV r32 48/31b eax upd L: 21.08ns= 42.2c T: 21.08ns= 42.17c 380 X86 :IDIV r32 31/31b eax upd L: 17.08ns= 34.2c T: 17.08ns= 34.17c 381 X86 :IDIV r32 16/31b eax/edx L: [no true dep.] T: 14.96ns= 29.92c 382 X86 :IDIV r32 0/31b L: [no true dep.] T: 16.25ns= 32.50c 383 X86 :IDIV r32 47/16b eax upd L: 23.08ns= 46.2c T: 23.08ns= 46.17c 384 X86 :IDIV r32 32/16b eax upd L: [no true dep.] T: 21.25ns= 42.50c 385 X86 :IDIV r32 16/16b eax upd L: 17.08ns= 34.2c T: 17.08ns= 34.17c 386 X86 :IDIV r32 0/16b L: [no true dep.] T: 16.25ns= 32.50c 387 X86 :IDIV r32 2^60/2^30 eax/edx L: [no true dep.] T: 19.00ns= 38.00c 388 X86 :IDIV r32 1/1 L: 17.33ns= 34.7c T: 16.25ns= 32.50c 389 X86 :IDIV r32 1/1 eax upd L: 17.08ns= 34.2c T: 17.08ns= 34.17c 390 X86 :IDIV r32 1/1 eax/edx upd L: 15.04ns= 30.1c T: 14.88ns= 29.75c 391 AMD64 :IDIV r64 126/63b (full) L: 53.50ns=107.0c T: 53.50ns=107.00c 392 AMD64 :IDIV r64 126/63b 0 rem. L: 53.50ns=107.0c T: 53.50ns=107.00c 393 AMD64 :IDIV r64 96/63b rax upd L: 49.00ns= 98.0c T: 48.54ns= 97.08c 394 AMD64 :IDIV r64 63/63b rax upd L: 23.33ns= 46.7c T: 23.33ns= 46.67c 395 AMD64 :IDIV r64 32/63b rax/rdx L: [no true dep.] T: 24.00ns= 48.00c 396 AMD64 :IDIV r64 0/63b L: [no true dep.] T: 24.50ns= 49.00c 397 AMD64 :IDIV r64 95/32b rax upd L: 54.50ns=109.0c T: 54.00ns=108.00c 398 AMD64 :IDIV r64 64/32b rax upd L: [no true dep.] T: 31.33ns= 62.67c 399 AMD64 :IDIV r64 32/32b rax upd L: 23.33ns= 46.7c T: 23.33ns= 46.67c 400 AMD64 :IDIV r64 0/32b L: [no true dep.] T: 24.50ns= 49.00c 401 AMD64 :IDIV r64 2^124/2^62 rax/rdx L: [no true dep.] T: 54.04ns=108.08c 402 AMD64 :IDIV r64 1/1 L: 23.58ns= 47.2c T: 23.58ns= 47.17c 403 AMD64 :IDIV r64 1/1 rax upd L: 23.33ns= 46.7c T: 23.33ns= 46.67c 404 AMD64 :IDIV r64 1/1 rax/rdx upd L: 24.00ns= 48.0c T: 24.00ns= 48.00c 405 X86 :DIV r8 16/ 8b (full) L: 11.75ns= 23.5c T: 11.75ns= 23.50c 406 X86 :DIV r8 12/ 8b ax upd L: 12.50ns= 25.0c T: 12.50ns= 25.00c 407 X86 :DIV r8 8/ 8b ax upd L: 12.50ns= 25.0c T: 12.50ns= 25.00c 408 X86 :DIV r8 4/ 8b ax upd L: [no true dep.] T: 12.50ns= 25.00c 409 X86 :DIV r8 0/ 8b L: [no true dep.] T: 12.00ns= 24.00c 410 X86 :DIV r8 12/ 4b ax upd L: 12.50ns= 25.0c T: 12.50ns= 25.00c 411 X86 :DIV r8 8/ 4b ax upd L: [no true dep.] T: 12.50ns= 25.00c 412 X86 :DIV r8 4/ 4b ax upd L: 12.50ns= 25.0c T: 12.50ns= 25.00c 413 X86 :DIV r8 0/ 4b L: [no true dep.] T: 12.00ns= 24.00c 414 X86 :DIV r8 2^14/2^7 ax upd L: [no true dep.] T: 12.50ns= 25.00c 415 X86 :DIV r8 1/1 L: 11.75ns= 23.5c T: 11.75ns= 23.50c 416 X86 :DIV r8 1/1 ax upd L: 12.50ns= 25.0c T: 12.50ns= 25.00c 417 X86 :DIV r16 32/16b (full) L: 15.00ns= 30.0c T: 14.75ns= 29.50c 418 X86 :DIV r16 30/15b 0 rem. L: 15.00ns= 30.0c T: 14.75ns= 29.50c 419 X86 :DIV r16 24/16b ax upd L: 15.25ns= 30.5c T: 15.25ns= 30.50c 420 X86 :DIV r16 16/16b ax upd L: 13.25ns= 26.5c T: 13.13ns= 26.25c 421 X86 :DIV r16 8/16b ax/dx upd L: [no true dep.] T: 13.25ns= 26.50c 422 X86 :DIV r16 0/16b L: [no true dep.] T: 12.75ns= 25.50c 423 X86 :DIV r16 24/ 8b ax upd L: 15.25ns= 30.5c T: 15.25ns= 30.50c 424 X86 :DIV r16 16/ 8b ax upd L: [no true dep.] T: 15.25ns= 30.50c 425 X86 :DIV r16 8/ 8b ax upd L: 13.25ns= 26.5c T: 13.17ns= 26.33c 426 X86 :DIV r16 0/ 8b L: [no true dep.] T: 12.75ns= 25.50c 427 X86 :DIV r16 1/1 L: 13.00ns= 26.0c T: 12.75ns= 25.50c 428 X86 :DIV r16 1/1 ax upd L: 13.25ns= 26.5c T: 13.25ns= 26.50c 429 X86 :DIV r16 1/1 ax/dx upd L: 13.29ns= 26.6c T: 13.25ns= 26.50c 430 X86 :DIV r32 64/32b (full) L: 19.00ns= 38.0c T: 18.75ns= 37.50c 431 X86 :DIV r32 62/31b 0 rem. L: 19.00ns= 38.0c T: 18.75ns= 37.50c 432 X86 :DIV r32 48/32b eax upd L: 16.75ns= 33.5c T: 16.75ns= 33.50c 433 X86 :DIV r32 32/32b eax upd L: 12.75ns= 25.5c T: 12.75ns= 25.50c 434 X86 :DIV r32 16/32b eax/edx L: [no true dep.] T: 9.50ns= 19.00c 435 X86 :DIV r32 0/32b L: [no true dep.] T: 18.75ns= 37.50c 436 X86 :DIV r32 48/16b eax upd L: 18.75ns= 37.5c T: 18.75ns= 37.50c 437 X86 :DIV r32 32/16b eax upd L: [no true dep.] T: 16.75ns= 33.50c 438 X86 :DIV r32 16/16b eax upd L: 12.75ns= 25.5c T: 12.75ns= 25.50c 439 X86 :DIV r32 0/16b L: [no true dep.] T: 12.75ns= 25.50c 440 X86 :DIV r32 2^62/2^31 eax/edx L: [no true dep.] T: 15.50ns= 31.00c 441 X86 :DIV r32 1/1 L: 13.00ns= 26.0c T: 12.75ns= 25.50c 442 X86 :DIV r32 1/1 eax upd L: 12.75ns= 25.5c T: 12.75ns= 25.50c 443 X86 :DIV r32 1/1 eax/edx upd L: 9.50ns= 19.0c T: 9.50ns= 19.00c 444 AMD64 :DIV r64 128/64b (full) L: 47.00ns= 94.0c T: 47.00ns= 94.00c 445 AMD64 :DIV r64 126/63b 0 rem. L: 47.00ns= 94.0c T: 47.00ns= 94.00c 446 AMD64 :DIV r64 96/64b rax upd L: 42.00ns= 84.0c T: 42.00ns= 84.00c 447 AMD64 :DIV r64 64/64b rax upd L: 12.29ns= 24.6c T: 12.25ns= 24.50c 448 AMD64 :DIV r64 32/64b rax/rdx L: [no true dep.] T: 12.58ns= 25.17c 449 AMD64 :DIV r64 0/64b L: [no true dep.] T: 18.29ns= 36.58c 450 AMD64 :DIV r64 96/32b rax upd L: 47.50ns= 95.0c T: 47.50ns= 95.00c 451 AMD64 :DIV r64 64/32b rax upd L: [no true dep.] T: 19.88ns= 39.75c 452 AMD64 :DIV r64 32/32b rax upd L: 12.29ns= 24.6c T: 12.25ns= 24.50c 453 AMD64 :DIV r64 0/32b L: [no true dep.] T: 18.29ns= 36.58c 454 AMD64 :DIV r64 2^126/2^63 rax/rdx L: [no true dep.] T: 47.50ns= 95.00c 455 AMD64 :DIV r64 1/1 L: 19.50ns= 39.0c T: 18.29ns= 36.58c 456 AMD64 :DIV r64 1/1 rax upd L: 12.29ns= 24.6c T: 12.25ns= 24.50c 457 AMD64 :DIV r64 1/1 rax/rdx upd L: 12.63ns= 25.3c T: 12.54ns= 25.08c 458 X86 :CBW L: 2.00ns= 4.0c T: 2.00ns= 4.00c 459 X86 :CWDE L: 0.50ns= 1.0c T: 0.50ns= 1.00c 460 AMD64 :CDQE L: 0.50ns= 1.0c T: 0.50ns= 1.00c 461 X86 :CWD L: 2.00ns= 4.0c T: 2.00ns= 4.00c 462 X86 :CDQ L: 0.50ns= 1.0c T: 0.50ns= 1.00c 463 AMD64 :CQO L: 0.50ns= 1.0c T: 0.50ns= 1.00c 464 X86 :CLC L: 0.50ns= 1.0c T: 0.50ns= 1.00c 465 X86 :STC L: 0.50ns= 1.0c T: 0.50ns= 1.00c 466 X86 :CMC L: 0.50ns= 1.0c T: 0.50ns= 1.00c 467 X86 :CLD L: 3.50ns= 7.0c T: 3.50ns= 7.00c 468 X86 :STD L: 17.50ns= 35.0c T: 17.50ns= 35.00c 475 LAHF :LAHF L: 0.50ns= 1.0c T: 0.50ns= 1.00c 476 LAHF :SAHF L: 0.50ns= 1.0c T: 0.50ns= 1.00c 483 X86 :PUSH r16 L: [no true dep.] T: 0.50ns= 1.00c 484 X86 :POP r16 L: [no true dep.] T: 2.50ns= 5.00c 485 X86 :PUSH r16 + POP r16 L: 4.00ns= 8.0c T: 4.00ns= 8.00c 486 AMD64 :PUSH r64 L: [no true dep.] T: 0.58ns= 1.17c 487 AMD64 :POP r64 L: [no true dep.] T: 0.50ns= 1.00c 488 AMD64 :PUSH r64 + POP r64 L: 2.54ns= 5.1c T: 1.00ns= 2.00c 489 AMD64 :PUSH imm8 L: [no true dep.] T: 0.54ns= 1.08c 490 AMD64 :PUSH imm8 + POP r64 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 491 AMD64 :PUSH imm32 L: [no true dep.] T: 0.50ns= 1.00c 492 AMD64 :PUSH imm32 + POP r64 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 493 X86 :PUSH [m16] L: [no true dep.] T: 2.50ns= 5.00c 494 X86 :POP [m16] L: [no true dep.] T: 3.00ns= 6.00c 495 X86 :PUSH [m16] + POP [m16] L: 5.50ns= 11.0c T: 5.50ns= 11.00c 496 AMD64 :PUSH [m64] L: [no true dep.] T: 2.50ns= 5.00c 497 AMD64 :POP [m64] L: [no true dep.] T: 3.00ns= 6.00c 498 AMD64 :PUSH [m64] + POP [m64] L: 5.50ns= 11.0c T: 5.50ns= 11.00c 499 X86 :PUSHF L: [no true dep.] T: 14.50ns= 29.00c 501 X86 :PUSHF + POPF L: 44.21ns= 88.4c T: 44.21ns= 88.42c 502 AMD64 :PUSHFQ L: [no true dep.] T: 14.50ns= 29.00c 504 AMD64 :PUSHFQ + POPFQ L: 36.00ns= 72.0c T: 36.00ns= 72.00c 505 X86 :CMPSB L: 3.00ns= 6.0c T: 3.00ns= 6.00c 506 X86 :CMPSW L: 3.00ns= 6.0c T: 3.00ns= 6.00c 507 X86 :CMPSD L: 3.00ns= 6.0c T: 3.00ns= 6.00c 508 AMD64 :CMPSQ L: 3.00ns= 6.0c T: 3.00ns= 6.00c 509 X86 :REPE CMPSB BW in L1D: 0.66 B/c 1328MiB/s 510 X86 :REPE CMPSW BW in L1D: 1.32 B/c 2647MiB/s 511 X86 :REPE CMPSD BW in L1D: 2.63 B/c 5257MiB/s 512 AMD64 :REPE CMPSQ BW in L1D: 5.18 B/c 10365MiB/s 513 X86 :LODSB L: 2.50ns= 5.0c T: 2.50ns= 5.00c 514 X86 :LODSW L: 2.50ns= 5.0c T: 2.50ns= 5.00c 515 X86 :LODSD L: 2.50ns= 5.0c T: 2.50ns= 5.00c 516 AMD64 :LODSQ L: 2.50ns= 5.0c T: 2.50ns= 5.00c 517 X86 :REP LODSB BW in L1D: 0.50 B/c 998MiB/s 518 X86 :REP LODSW BW in L1D: 0.99 B/c 1989MiB/s 519 X86 :REP LODSD BW in L1D: 1.99 B/c 3973MiB/s 520 AMD64 :REP LODSQ BW in L1D: 3.91 B/c 7815MiB/s 521 X86 :STOSB L: 2.04ns= 4.1c T: 2.00ns= 4.00c 522 X86 :STOSW L: 2.04ns= 4.1c T: 2.00ns= 4.00c 523 X86 :STOSD L: 2.04ns= 4.1c T: 2.00ns= 4.00c 524 AMD64 :STOSQ L: 2.04ns= 4.1c T: 2.00ns= 4.00c 525 X86 :REP STOSB BW in L1D:13.76 B/c 27520MiB/s 526 X86 :REP STOSW BW in L1D:12.26 B/c 24526MiB/s 527 X86 :REP STOSD BW in L1D:14.04 B/c 28070MiB/s 528 AMD64 :REP STOSQ BW in L1D:13.36 B/c 26712MiB/s 529 X86 :MOVSB L: 3.00ns= 6.0c T: 3.00ns= 6.00c 530 X86 :MOVSW L: 3.00ns= 6.0c T: 3.00ns= 6.00c 531 X86 :MOVSD L: 3.00ns= 6.0c T: 3.00ns= 6.00c 532 AMD64 :MOVSQ L: 3.00ns= 6.0c T: 3.00ns= 6.00c 533 X86 :REP MOVSB BW in L1D:13.15 B/c 26298MiB/s 534 X86 :REP MOVSW BW in L1D:13.56 B/c 27110MiB/s 535 X86 :REP MOVSD BW in L1D:13.50 B/c 26991MiB/s 536 AMD64 :REP MOVSQ BW in L1D:13.18 B/c 26354MiB/s 537 X86 :SCASB L: 2.50ns= 5.0c T: 2.50ns= 5.00c 538 X86 :SCASW L: 2.50ns= 5.0c T: 2.50ns= 5.00c 539 X86 :SCASD L: 2.50ns= 5.0c T: 2.50ns= 5.00c 540 AMD64 :SCASQ L: 2.50ns= 5.0c T: 2.50ns= 5.00c 541 X86 :REPNE SCASB BW in L1D: 0.33 B/c 666MiB/s 542 X86 :REPNE SCASW BW in L1D: 0.67 B/c 1332MiB/s 543 X86 :REPNE SCASD BW in L1D: 1.33 B/c 2662MiB/s 544 AMD64 :REPNE SCASQ BW in L1D: 2.66 B/c 5316MiB/s 545 X86 :XADD r8, r8 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 546 X86 :XADD r16, r16 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 547 X86 :XADD r32, r32 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 548 AMD64 :XADD r64, r64 L: 2.50ns= 5.0c T: 2.50ns= 5.00c 549 X86 :CMPXCHG r8, r8 L: 5.50ns= 11.0c T: 5.50ns= 11.00c 550 X86 :CMPXCHG r16, r16 L: 3.00ns= 6.0c T: 3.00ns= 6.00c 551 X86 :CMPXCHG r32, r32 L: 3.00ns= 6.0c T: 3.00ns= 6.00c 552 AMD64 :CMPXCHG r64, r64 L: 3.00ns= 6.0c T: 3.00ns= 6.00c 553 CMPX8 :CMPXCHG8B L: 7.00ns= 14.0c T: 7.00ns= 14.00c 554 CMPX16 :CMPXCHG16B L: 12.08ns= 24.2c T: 9.00ns= 18.00c 555 X86 :RDTSC L: [no true dep.] T: 17.50ns= 35.00c 556 X86 :CPUID (EAX = 0) L: 27.00ns= 54.0c T: 27.00ns= 54.00c 557 X86 :CPUID (EAX = 1) L: 54.00ns=108.0c T: 54.00ns=108.00c 558 POPCNT :POPCNT r16, r16 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 559 POPCNT :POPCNT r32, r32 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 560 POPCNT :POPCNT r64, r64 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 564 SSE4.2 :CRC32 r32, r8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 565 SSE4.2 :CRC32 r32, r16 L: 3.04ns= 6.1c T: 3.00ns= 6.00c 566 SSE4.2 :CRC32 r32, r32 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 567 SSE4.2 :CRC32 r64, r8 L: 3.04ns= 6.1c T: 3.00ns= 6.00c 568 SSE4.2 :CRC32 r64, r16 L: 3.04ns= 6.1c T: 3.00ns= 6.00c 569 X87 :FNOP L: [no true dep.] T: 0.25ns= 0.50c 570 X87 :FXCH st(i) L: 0.50ns= 1.0c T: 0.50ns= 1.00c 571 X87 :FCHS L: 0.50ns= 1.0c T: 0.50ns= 1.00c 572 X87 :FABS L: 0.50ns= 1.0c T: 0.50ns= 1.00c 573 X87 :FTST L: [no true dep.] T: 0.50ns= 1.00c 574 X87 :FXAM L: [no true dep.] T: 0.50ns= 1.00c 575 CMOV :FCMOVE st, st(i) L: 3.00ns= 6.0c T: 3.00ns= 6.00c 576 X87 :FADD st(i), st (st = 0.0) L: 1.50ns= 3.0c T: 0.50ns= 1.00c 577 X87 :FADD st(i), st L: 1.50ns= 3.0c T: 0.50ns= 1.00c 578 X87 :FADD st, st(i), FXCH st(i) L: 2.00ns= 4.0c T: 2.00ns= 4.00c 579 X87 :FMUL st(i), st (st = 0.0) L: 2.50ns= 5.0c T: 1.00ns= 2.00c 580 X87 :FMUL st(i), st L: 2.50ns= 5.0c T: 1.00ns= 2.00c 581 X87 :FMUL st, st(i), FXCH st(i) L: 3.00ns= 6.0c T: 3.00ns= 6.00c 582 X87 :FMUL + FADD st, st(i) L: 4.00ns= 8.0c T: [not enough reg] 583 X87 :FMUL st(2i) FADD st(2i+1) L: 2.50ns= 5.0c T: [not enough reg] 584 X87 :FDIV32 st(i), st L: 9.50ns= 19.0c T: 8.50ns= 17.00c 585 X87 :FDIV64 st(i), st L: 17.00ns= 34.0c T: 16.00ns= 32.00c 586 X87 :FDIV80 st(i), st L: 19.50ns= 39.0c T: 18.50ns= 37.00c 587 X87 :FDIV80 (0.0l/x) L: 6.50ns= 13.0c T: 5.50ns= 11.00c 588 X87 :FDIV80 (x/1.0l) L: 19.50ns= 39.0c T: 18.50ns= 37.00c 589 X87 :FDIV80 (x/2.0l) L: 19.50ns= 39.0c T: 18.50ns= 37.00c 590 X87 :FDIV80 (x/0.5l) L: 19.50ns= 39.0c T: 18.50ns= 37.00c 591 X87 :FSQRT32 st L: 10.00ns= 20.0c T: 10.50ns= 21.00c 592 X87 :FSQRT64 st L: 17.50ns= 35.0c T: 18.00ns= 36.00c 593 X87 :FSQRT80 st L: 20.00ns= 40.0c T: 20.50ns= 41.00c 594 X87 :FSQRT80 (0.0l) L: 6.50ns= 13.0c T: 7.00ns= 14.00c 595 X87 :FSQRT80 (1.0l) L: 20.00ns= 40.0c T: 20.50ns= 41.00c 596 X87 :FDECSTP L: [no true dep.] T: 0.25ns= 0.50c 597 X87 :FINCSTP L: [no true dep.] T: 0.25ns= 0.50c 598 X87 :FCOM st(i) L: [no true dep.] T: 0.50ns= 1.00c 599 CMOV :FCOMI st, st(i) L: [no true dep.] T: 0.50ns= 1.00c 600 X87 :FSIN80 (0.0) L: 21.00ns= 42.0c T: 22.25ns= 44.50c 601 X87 :FSIN80 (0.0) + FADD L: 22.13ns= 44.3c T: 21.25ns= 42.50c 602 X87 :FSIN80 (1.0) + FADD L: 74.25ns=148.5c T: 72.88ns=145.75c 603 X87 :FSIN80 (4Pi) + FADD L: 62.50ns=125.0c T: 63.00ns=126.00c 604 X87 :FSIN80 (2Pi) + FADD L: 62.50ns=125.0c T: 63.04ns=126.08c 605 X87 :FSIN80 (Pi) + FADD L: 62.00ns=124.0c T: 62.50ns=125.00c 606 X87 :FSIN80 (Pi/2) + FADD L: 66.50ns=133.0c T: 67.00ns=134.00c 607 X87 :FSIN80 (Pi/4) + FADD L: 87.50ns=175.0c T: 88.00ns=176.00c 608 X87 :FSIN80 (Pi/8) + FADD L: 78.00ns=156.0c T: 78.50ns=157.00c 609 X87 :FSIN80 (Pi/16) + FADD L: 77.00ns=154.0c T: 77.54ns=155.08c 610 X87 :FSIN80 (Pi/32) + FADD L: 77.00ns=154.0c T: 77.50ns=155.00c 611 X87 :FCOS80 (0.73908513...) L: 84.00ns=168.0c T: 84.55ns=169.08c 612 X87 :FCOS80 (0.73908513...)+FADD L: 85.50ns=171.0c T: 86.50ns=173.00c 613 X87 :FCOS80 (0.0) + FADD L: 22.75ns= 45.5c T: 22.21ns= 44.42c 614 X87 :FCOS80 (1.0) + FADD L: 60.50ns=121.0c T: 61.50ns=123.00c 615 X87 :FCOS80 (4Pi) + FADD L: 65.00ns=130.0c T: 65.00ns=130.00c 616 X87 :FCOS80 (2Pi) + FADD L: 65.00ns=130.0c T: 65.00ns=130.00c 617 X87 :FCOS80 (Pi) + FADD L: 64.50ns=129.0c T: 64.50ns=129.00c 618 X87 :FCOS80 (Pi/2) + FADD L: 60.00ns=120.0c T: 60.00ns=120.00c 619 X87 :FCOS80 (Pi/4) + FADD L: 76.00ns=152.0c T: 76.54ns=153.08c 620 X87 :FCOS80 (Pi/8) + FADD L: 85.50ns=171.0c T: 86.55ns=173.08c 621 X87 :FCOS80 (Pi/16) + FADD L: 79.50ns=159.0c T: 80.00ns=160.00c 622 X87 :FCOS80 (Pi/32) + FADD L: 79.50ns=159.0c T: 80.00ns=160.00c 623 MMX :EMMS L: 5.00ns= 10.0c T: 5.00ns= 10.00c 624 MMX :MOVD r32, mm L: [diff. reg. set] T: 0.50ns= 1.00c 625 MMX :MOVD mm, r32 L: [diff. reg. set] T: 0.50ns= 1.00c 626 MMX :MOVD r32, mm+MOVD mm, r32 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 627 AMD64 :MOVD r64, mm L: [diff. reg. set] T: 0.50ns= 1.00c 628 AMD64 :MOVD mm, r64 L: [diff. reg. set] T: 0.50ns= 1.00c 629 AMD64 :MOVD r64, mm+MOVD mm, r64 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 630 MMX :MOVD mm, [m32] L: [memory dep.] T: 0.50ns= 1.00c 631 MMX :MOVD [m32], mm L: [memory dep.] T: 0.50ns= 1.00c 632 MMX :MOVD mm,[m32]+MOVD [m32],mm L: 3.50ns= 7.0c T: 1.00ns= 2.00c 633 MMX :MOVQ mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 634 MMX :MOVQ mm, [m64] L: [memory dep.] T: 0.50ns= 1.00c 635 MMX :MOVQ [m64], mm L: [memory dep.] T: 0.50ns= 1.00c 636 MMX :MOVQ mm,[m64]+MOVQ [m64],mm L: 3.50ns= 7.0c T: 1.00ns= 2.00c 637 SSE :MOVNTQ [m64], mm L: [memory dep.] T: 1.00ns= 1.00c 638 SSE :PMOVMSKB r32, mm L: [diff. reg. set] T: 0.50ns= 1.00c 639 AMD64 :PMOVMSKB r64, mm L: [diff. reg. set] T: 0.50ns= 1.00c 640 SSE :MASKMOVQ mm, mm L: [memory dep.] T: 1.00ns= 1.00c 641 MMX :PADDB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 642 MMX :PADDW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 643 MMX :PADDD mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 644 SSE2 :PADDQ mm, mm L: 2.00ns= 4.0c T: 2.00ns= 4.00c 645 MMX :PADDSB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 646 MMX :PADDSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 647 MMX :PADDUSB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 648 MMX :PADDUSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 649 MMX :PSUBB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 650 MMX :PSUBB mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 651 MMX :PSUBW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 652 MMX :PSUBW mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 653 MMX :PSUBD mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 654 MMX :PSUBD mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 655 SSE2 :PSUBQ mm, mm L: 2.00ns= 4.0c T: 2.00ns= 4.00c 656 SSE2 :PSUBQ mm1, mm2 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 657 MMX :PSUBSB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 658 MMX :PSUBSB mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 659 MMX :PSUBSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 660 MMX :PSUBSW mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 661 MMX :PSUBUSB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 662 MMX :PSUBUSB mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 663 MMX :PSUBUSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 664 MMX :PSUBUSW mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 665 MMX :PCMPEQB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 666 MMX :PCMPEQB mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 667 MMX :PCMPEQW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 668 MMX :PCMPEQW mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 669 MMX :PCMPEQD mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 670 MMX :PCMPEQD mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 671 MMX :PCMPGTB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 672 MMX :PCMPGTB mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 673 MMX :PCMPGTW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 674 MMX :PCMPGTW mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 675 MMX :PCMPGTD mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 676 MMX :PCMPGTD mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 677 MMX :PAND mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 678 MMX :PAND mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 679 MMX :PANDN mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 680 MMX :PANDN mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 681 MMX :POR mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 682 MMX :POR mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 683 MMX :PXOR mm, mm L: 0.25ns= 0.5c T: 0.25ns= 0.50c 684 MMX :PXOR mm1, mm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 685 MMX :PMULHW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 686 SSE :PMULHUW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 688 SSSE3 :PMULHRSW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 689 MMX :PMULLW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 690 SSE2 :PMULUDQ mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 691 SSSE3 :PMADDUBSW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 692 MMX :PMADDWD mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 693 MMX :PSLLW mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 694 MMX :PSLLW mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 695 MMX :PSLLD mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 696 MMX :PSLLD mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 697 MMX :PSLLQ mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 698 MMX :PSLLQ mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 699 MMX :PSRAW mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 700 MMX :PSRAW mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 701 MMX :PSRAD mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 702 MMX :PSRAD mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 703 MMX :PSRLW mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 704 MMX :PSRLW mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 705 MMX :PSRLD mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 706 MMX :PSRLD mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 707 MMX :PSRLQ mm, mm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 708 MMX :PSRLQ mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 709 MMX :PUNPCKHBW mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 710 MMX :PUNPCKHWD mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 711 MMX :PUNPCKHDQ mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 712 MMX :PUNPCKLBW mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 713 MMX :PUNPCKLWD mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 714 MMX :PUNPCKLDQ mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 715 MMX :PACKSSWB mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 716 MMX :PACKUSWB mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 717 MMX :PACKSSDW mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 746 3DNOWPREF :PREFETCHW [mem] L: [memory dep.] T: 0.50ns= 1.00c 753 SSE :PAVGB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 754 SSE :PAVGW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 755 SSE :PEXTRW r32, mm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 756 SSE :PINSRW mm, r32, im8 L: [diff. reg. set] T: 0.50ns= 1.00c 757 SSE :PEXTRW + PINSRW r32 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 758 AMD64 :PEXTRW r64, mm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 759 AMD64 :PINSRW mm, r64, im8 L: [diff. reg. set] T: 0.50ns= 1.00c 760 AMD64 :PEXTRW + PINSRW r64 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 761 SSE :PMAXSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 762 SSE :PMAXUB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 763 SSE :PMINSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 764 SSE :PMINUB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 765 SSE :PSADBW mm, mm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 766 SSE :PSHUFW mm, mm, im8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 767 SSE :PREFETCHNTA [mem] L: [memory dep.] T: 0.50ns= 1.00c 768 SSE :PREFETCHT0 [mem] L: [memory dep.] T: 0.50ns= 1.00c 769 SSE :PREFETCHT1 [mem] L: [memory dep.] T: 0.50ns= 1.00c 770 SSE :PREFETCHT2 [mem] L: [memory dep.] T: 0.50ns= 1.00c 771 SSE :SFENCE L: 3.25ns= 6.5c T: 3.25ns= 6.50c 772 SSE2 :LFENCE L: 4.00ns= 8.0c T: 4.00ns= 8.00c 773 SSE2 :MFENCE L: 6.50ns= 13.0c T: 6.50ns= 13.00c 774 SSSE3 :PABSB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 775 SSSE3 :PABSW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 776 SSSE3 :PABSD mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 777 SSSE3 :PALIGNR mm, mm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 778 SSSE3 :PHADDW mm, mm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 779 SSSE3 :PHADDD mm, mm L: 2.50ns= 5.0c T: 2.50ns= 5.00c 780 SSSE3 :PHADDSW mm, mm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 781 SSSE3 :PHSUBW mm, mm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 782 SSSE3 :PHSUBD mm, mm L: 2.50ns= 5.0c T: 2.50ns= 5.00c 783 SSSE3 :PHSUBSW mm, mm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 784 SSSE3 :PSHUFB mm, mm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 785 SSSE3 :PSIGNB mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 786 SSSE3 :PSIGNW mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 787 SSSE3 :PSIGND mm, mm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 788 SSE :MOVHLPS xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 789 SSE :MOVHLPS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 792 SSE :MOVSS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 794 SSE :MOVSS xmm, [m32] L: [memory dep.] T: 0.50ns= 1.00c 795 SSE :MOVSS [m32], xmm L: [memory dep.] T: 0.50ns= 1.00c 796 SSE :MOVSS LS pair L: 3.42ns= 6.8c T: 1.00ns= 2.00c 800 SSE :MOVLPS xmm, [m32] L: [memory dep.] T: 0.50ns= 1.00c 801 SSE :MOVLPS [m32], xmm L: [memory dep.] T: 0.50ns= 1.00c 802 SSE :MOVLPS LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 806 SSE :MOVHPS xmm, [m32] L: [memory dep.] T: 0.50ns= 1.00c 807 SSE :MOVHPS [m32], xmm L: [memory dep.] T: 0.50ns= 1.00c 808 SSE :MOVHPS LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 812 SSE :MOVAPS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 813 SSE :MOVAPS xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 814 SSE :MOVAPS [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 815 SSE :MOVAPS LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 820 SSE :MOVUPS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 821 SSE :MOVUPS xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 822 SSE :MOVUPS [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 823 SSE :MOVUPS aligned LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 824 SSE :MOVUPS xmm, [m128 + 4] L: [memory dep.] T: 0.50ns= 1.00c 825 SSE :MOVUPS [m128 + 4], xmm L: [memory dep.] T: 0.58ns= 1.17c 826 SSE :MOVUPS unaligned LS pair L: 3.46ns= 6.9c T: 1.00ns= 2.00c 835 SSE :MOVNTPS [m128], xmm L: [memory dep.] T: 1.00ns= 1.00c 837 SSE :MOVMSKPS r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 842 SSE :UNPCKLPS xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 844 SSE :UNPCKHPS xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 846 SSE :SHUFPS xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 850 SSE :COMISS xmm, xmm L: [no true dep.] T: 0.50ns= 1.00c 852 SSE :UCOMISS xmm, xmm L: [no true dep.] T: 0.50ns= 1.00c 854 SSE :CMPSS xmm, xmm, imm8 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 855 SSE :CMPPS xmm, xmm, imm8 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 858 SSE :SUBSS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 860 SSE :SUBPS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 862 SSE :ADDSS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 864 SSE :ADDPS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 866 SSE :MULSS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 868 SSE :MULPS xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 870 SSE :MULSS+ADDSS xmm, xmm L: 3.50ns= 7.0c T: 0.79ns= 1.58c 872 SSE :MULPS+ADDPS xmm, xmm L: 4.00ns= 8.0c T: 1.00ns= 2.00c 874 SSE :MULSS xm1,xm1 ADDSS xm2,xm2 L: 2.00ns= 4.0c T: 0.50ns= 1.00c 876 SSE :MULPS xm1,xm1 ADDPS xm2,xm2 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 878 SSE :MAXSS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 880 SSE :MAXPS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 882 SSE :MINSS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 884 SSE :MINPS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 886 SSE :ANDNPS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 887 SSE :ANDNPS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 890 SSE :ANDPS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 891 SSE :ANDPS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 894 SSE :ORPS xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 895 SSE :ORPS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 898 SSE :XORPS xmm, xmm L: 0.25ns= 0.5c T: 0.25ns= 0.50c 899 SSE :XORPS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 902 SSE :DIVSS xmm, xmm L: 9.50ns= 19.0c T: 8.50ns= 17.00c 903 SSE :DIVSS (0.0f/x) L: 6.50ns= 13.0c T: 5.50ns= 11.00c 904 SSE :DIVSS (x/1.0f) L: 9.50ns= 19.0c T: 8.50ns= 17.00c 905 SSE :DIVSS (x/2.0f) L: 9.50ns= 19.0c T: 8.50ns= 17.00c 906 SSE :DIVSS (x/0.5f) L: 9.50ns= 19.0c T: 8.50ns= 17.00c 912 SSE :DIVPS xmm, xmm L: 19.50ns= 39.0c T: 19.50ns= 39.00c 913 SSE :DIVPS (0.0f/x) L: 13.50ns= 27.0c T: 13.50ns= 27.00c 914 SSE :DIVPS (x/1.0f) L: 19.50ns= 39.0c T: 19.50ns= 39.00c 915 SSE :DIVPS (x/2.0f) L: 19.50ns= 39.0c T: 19.50ns= 39.00c 916 SSE :DIVPS (x/0.5f) L: 19.50ns= 39.0c T: 19.50ns= 39.00c 922 SSE :SQRTSS xmm, xmm L: 10.00ns= 20.0c T: 9.00ns= 18.00c 923 SSE :SQRTSS (0.0f) L: 6.50ns= 13.0c T: 5.50ns= 11.00c 924 SSE :SQRTSS (1.0f) L: 10.00ns= 20.0c T: 9.00ns= 18.00c 928 SSE :SQRTPS xmm, xmm L: 20.00ns= 40.0c T: 20.00ns= 40.00c 929 SSE :SQRTPS (0.0f) L: 13.00ns= 26.0c T: 13.00ns= 26.00c 930 SSE :SQRTPS (1.0f) L: 20.00ns= 40.0c T: 20.00ns= 40.00c 934 SSE :RCPSS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 936 SSE :RCPPS xmm, xmm L: 4.50ns= 9.0c T: 4.00ns= 8.00c 938 SSE :RSQRTSS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 940 SSE :RSQRTPS xmm, xmm L: 4.50ns= 9.0c T: 4.00ns= 8.00c 942 SSE :CVTPI2PS xmm, mm L: [diff. reg. set] T: 0.50ns= 1.00c 943 SSE :CVTPS2PI mm, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 944 SSE :CVTPS2PI + CVTPI2PS L: 4.00ns= 8.0c T: 2.50ns= 5.00c 945 SSE :CVTTPS2PI mm, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 946 SSE :CVTTPS2PI + CVTPI2PS L: 4.00ns= 8.0c T: 2.50ns= 5.00c 947 SSE :CVTSI2SS xmm, r32 L: [diff. reg. set] T: 0.50ns= 1.00c 948 SSE :CVTSS2SI r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 949 SSE :CVTSS2SI + CVTSI2SS r32 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 950 SSE :CVTTSS2SI r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 951 SSE :CVTTSS2SI + CVTSI2SS r32 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 957 AMD64 :CVTSI2SS xmm, r64 L: [diff. reg. set] T: 0.50ns= 1.00c 958 AMD64 :CVTSS2SI r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 959 AMD64 :CVTSS2SI + CVTSI2SS r64 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 960 AMD64 :CVTTSS2SI r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 961 AMD64 :CVTTSS2SI + CVTSI2SS r64 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 967 SSE :STMXCSR [mem] L: [memory dep.] T: 5.50ns= 11.00c 968 SSE :LDMXCSR [mem] L: [memory dep.] T: 4.00ns= 8.00c 969 SSE :STMXCSR + LDMXCSR L: 11.00ns= 22.0c T: 10.79ns= 21.58c 970 SSE2 :MOVSD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 971 SSE2 :MOVSD xmm, [m64] L: [memory dep.] T: 0.50ns= 1.00c 972 SSE2 :MOVSD [m64], xmm L: [memory dep.] T: 0.50ns= 1.00c 973 SSE2 :MOVSD LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 978 SSE2 :MOVLPD xmm, [m64] L: [memory dep.] T: 0.50ns= 1.00c 979 SSE2 :MOVLPD [m64], xmm L: [memory dep.] T: 0.50ns= 1.00c 980 SSE2 :MOVLPD LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 984 SSE2 :MOVHPD xmm, [m64] L: [memory dep.] T: 0.50ns= 1.00c 985 SSE2 :MOVHPD [m64], xmm L: [memory dep.] T: 0.50ns= 1.00c 986 SSE2 :MOVHPD LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 990 SSE2 :MOVAPD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 991 SSE2 :MOVAPD xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 992 SSE2 :MOVAPD [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 993 SSE2 :MOVAPD LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 998 SSE2 :MOVUPD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 999 SSE2 :MOVUPD xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 1000 SSE2 :MOVUPD [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 1001 SSE2 :MOVUPD aligned LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 1002 SSE2 :MOVUPD xmm, [m128 + 4] L: [memory dep.] T: 0.50ns= 1.00c 1003 SSE2 :MOVUPD [m128 + 4], xmm L: [memory dep.] T: 0.58ns= 1.17c 1004 SSE2 :MOVUPD unaligned LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 1013 SSE2 :MOVNTPD [m128], xmm L: [memory dep.] T: 1.00ns= 1.00c 1015 SSE2 :MOVMSKPD r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1020 SSE2 :UNPCKLPD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1022 SSE2 :UNPCKHPD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1024 SSE2 :SHUFPD xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1028 SSE2 :COMISD xmm, xmm L: [no true dep.] T: 0.50ns= 1.00c 1030 SSE2 :UCOMISD xmm, xmm L: [no true dep.] T: 0.50ns= 1.00c 1032 SSE2 :CMPSD xmm, xmm, imm8 L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1033 SSE2 :CMPPD xmm, xmm, imm8 L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1036 SSE2 :SUBSD xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1038 SSE2 :SUBPD xmm, xmm L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1040 SSE2 :ADDSD xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1042 SSE2 :ADDPD xmm, xmm L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1044 SSE2 :MULSD xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1046 SSE2 :MULPD xmm, xmm L: 3.50ns= 7.0c T: 2.00ns= 4.00c 1048 SSE2 :MULSD+ADDSD xmm, xmm L: 4.00ns= 8.0c T: 1.04ns= 2.08c 1050 SSE2 :MULPD+ADDPD xmm, xmm L: 5.50ns= 11.0c T: 2.00ns= 4.00c 1052 SSE2 :MULSD xm1,xm1 ADDSD xm2,xm2 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1054 SSE2 :MULPD xm1,xm1 ADDPD xm2,xm2 L: 3.50ns= 7.0c T: 2.00ns= 4.00c 1056 SSE2 :MAXSD xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1058 SSE2 :MAXPD xmm, xmm L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1060 SSE2 :MINSD xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1062 SSE2 :MINPD xmm, xmm L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1064 SSE2 :ANDNPD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1065 SSE2 :ANDNPD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1068 SSE2 :ANDPD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1069 SSE2 :ANDPD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1072 SSE2 :ORPD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1073 SSE2 :ORPD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1076 SSE2 :XORPD xmm, xmm L: 0.25ns= 0.5c T: 0.25ns= 0.50c 1077 SSE2 :XORPD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1080 SSE2 :DIVSD xmm, xmm L: 17.00ns= 34.0c T: 16.00ns= 32.00c 1081 SSE2 :DIVSD (0.0/x) L: 6.50ns= 13.0c T: 5.50ns= 11.00c 1082 SSE2 :DIVSD (x/1.0) L: 17.00ns= 34.0c T: 16.00ns= 32.00c 1083 SSE2 :DIVSD (x/2.0) L: 17.00ns= 34.0c T: 16.00ns= 32.00c 1084 SSE2 :DIVSD (x/0.5) L: 17.00ns= 34.0c T: 16.00ns= 32.00c 1090 SSE2 :DIVPD xmm, xmm L: 34.50ns= 69.0c T: 34.50ns= 69.00c 1091 SSE2 :DIVPD (0.0/x) L: 13.50ns= 27.0c T: 13.50ns= 27.00c 1092 SSE2 :DIVPD (x/1.0) L: 34.50ns= 69.0c T: 34.50ns= 69.00c 1093 SSE2 :DIVPD (x/2.0) L: 34.50ns= 69.0c T: 34.50ns= 69.00c 1094 SSE2 :DIVPD (x/0.5) L: 34.50ns= 69.0c T: 34.50ns= 69.00c 1100 SSE2 :SQRTSD xmm, xmm L: 17.50ns= 35.0c T: 16.50ns= 33.00c 1101 SSE2 :SQRTSD (0.0) L: 6.50ns= 13.0c T: 5.50ns= 11.00c 1102 SSE2 :SQRTSD (1.0) L: 17.50ns= 35.0c T: 16.50ns= 33.00c 1106 SSE2 :SQRTPD xmm, xmm L: 35.00ns= 70.0c T: 35.00ns= 70.00c 1107 SSE2 :SQRTPD (0.0) L: 13.00ns= 26.0c T: 13.00ns= 26.00c 1108 SSE2 :SQRTPD (1.0) L: 35.00ns= 70.0c T: 35.00ns= 70.00c 1112 SSE2 :CVTPI2PD xmm, mm L: [diff. reg. set] T: 1.00ns= 2.00c 1113 SSE2 :CVTPD2PI mm, xmm L: [diff. reg. set] T: 1.00ns= 2.00c 1114 SSE2 :CVTPD2PI + CVTPI2PD L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1115 SSE2 :CVTTPD2PI mm, xmm L: [diff. reg. set] T: 1.00ns= 2.00c 1116 SSE2 :CVTTPD2PI + CVTPI2PD L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1117 SSE2 :CVTSI2SD xmm, r32 L: [diff. reg. set] T: 0.50ns= 1.00c 1118 SSE2 :CVTSD2SI r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1119 SSE2 :CVTSD2SI + CVTSI2SD r32 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1120 SSE2 :CVTTSD2SI r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1121 SSE2 :CVTTSD2SI + CVTSI2SD r32 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1127 AMD64 :CVTSI2SD xmm, r64 L: [diff. reg. set] T: 0.50ns= 1.00c 1128 AMD64 :CVTSD2SI r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1129 AMD64 :CVTSD2SI + CVTSI2SD r64 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1130 AMD64 :CVTTSD2SI r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1131 AMD64 :CVTTSD2SI + CVTSI2SD r64 L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1137 SSE2 :CVTDQ2PD xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1138 SSE2 :CVTPD2DQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1139 SSE2 :CVTPD2DQ + CVTDQ2PD L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1140 SSE2 :CVTTPD2DQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1141 SSE2 :CVTTPD2DQ + CVTDQ2PD L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1147 SSE2 :CVTDQ2PS xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1148 SSE2 :CVTPS2DQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1149 SSE2 :CVTPS2DQ + CVTDQ2PS L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1150 SSE2 :CVTTPS2DQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1151 SSE2 :CVTTPS2DQ + CVTDQ2PS L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1157 SSE2 :CVTPS2PD xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1158 SSE2 :CVTPD2PS xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1159 SSE2 :CVTPD2PS + CVTPS2PD L: 5.00ns= 10.0c T: 3.50ns= 7.00c 1160 SSE2 :CVTSS2SD xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1161 SSE2 :CVTSD2SS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1162 SSE2 :CVTSD2SS + CVTSS2SD L: 4.00ns= 8.0c T: 2.50ns= 5.00c 1169 SSE2 :MOVD r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1170 SSE2 :MOVD xmm, r32 L: [diff. reg. set] T: 0.50ns= 1.00c 1171 SSE2 :MOVD r32, xmm+MOVD xmm, r32 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 1175 AMD64 :MOVD r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1176 AMD64 :MOVD xmm, r64 L: [diff. reg. set] T: 0.50ns= 1.00c 1177 AMD64 :MOVD r64, xmm+MOVD xmm, r64 L: 3.50ns= 7.0c T: 3.50ns= 7.00c 1181 SSE2 :MOVD xmm, [m32] L: [memory dep.] T: 0.50ns= 1.00c 1182 SSE2 :MOVD [m32], xmm L: [memory dep.] T: 0.50ns= 1.00c 1183 SSE2 :MOVD LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 1187 SSE2 :MOVQ xmm, [m64] L: [memory dep.] T: 0.50ns= 1.00c 1188 SSE2 :MOVQ [m64], xmm L: [memory dep.] T: 0.50ns= 1.00c 1189 SSE2 :MOVQ LS pair L: 3.38ns= 6.8c T: 1.00ns= 2.00c 1193 SSE2 :MOVDQ2Q mm, xmm L: [diff. reg. set] T: 0.25ns= 0.50c 1194 SSE2 :MOVQ2DQ xmm, mm L: [diff. reg. set] T: 0.25ns= 0.50c 1195 SSE2 :MOVDQ2Q + MOVQ2DQ xmm, mm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1196 SSE2 :MOVDQA xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1197 SSE2 :MOVDQA xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 1198 SSE2 :MOVDQA [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 1199 SSE2 :MOVDQA LS pair L: 3.29ns= 6.6c T: 1.00ns= 2.00c 1204 SSE2 :MOVDQU xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1205 SSE2 :MOVDQU xmm, [m128] L: [memory dep.] T: 0.50ns= 1.00c 1206 SSE2 :MOVDQU [m128], xmm L: [memory dep.] T: 0.50ns= 1.00c 1207 SSE2 :MOVDQU aligned LS pair L: 3.46ns= 6.9c T: 1.00ns= 2.00c 1208 SSE2 :MOVDQU xmm, [m128 + 4] L: [memory dep.] T: 0.50ns= 1.00c 1209 SSE2 :MOVDQU [m128 + 4], xmm L: [memory dep.] T: 0.58ns= 1.17c 1210 SSE2 :MOVDQU unaligned LS pair L: 3.50ns= 7.0c T: 1.00ns= 2.00c 1218 SSE4.1 :MOVNTDQA xmm, [m128] L: [memory dep.] T: 1.00ns= 1.00c 1219 SSE2 :MOVNTDQ [m128], xmm L: [memory dep.] T: 1.00ns= 1.00c 1220 SSE4.1 :MOVNTDQA + MOVNTDQ L: 157.09ns=314.2c T: 314.17ns=314.17c 1224 SSE2 :PMOVMSKB r32, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1225 AMD64 :PMOVMSKB r64, xmm L: [diff. reg. set] T: 0.50ns= 1.00c 1228 SSE2 :MASKMOVDQU xmm, xmm L: [memory dep.] T: 5.00ns= 5.00c 1230 SSE2 :PADDB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1232 SSE2 :PADDW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1234 SSE2 :PADDD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1236 SSE2 :PADDQ xmm, xmm L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1238 SSE2 :PADDSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1240 SSE2 :PADDSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1242 SSE2 :PADDUSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1244 SSE2 :PADDUSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1246 SSE2 :PSUBB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1247 SSE2 :PSUBB xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1250 SSE2 :PSUBW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1251 SSE2 :PSUBW xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1254 SSE2 :PSUBD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1255 SSE2 :PSUBD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1258 SSE2 :PSUBQ xmm, xmm L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1259 SSE2 :PSUBQ xmm1, xmm2 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1262 SSE2 :PSUBSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1263 SSE2 :PSUBSB xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1266 SSE2 :PSUBSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1267 SSE2 :PSUBSW xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1270 SSE2 :PSUBUSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1271 SSE2 :PSUBUSB xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1274 SSE2 :PSUBUSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1275 SSE2 :PSUBUSW xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1278 SSE2 :PCMPEQB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1279 SSE2 :PCMPEQB xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1282 SSE2 :PCMPEQW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1283 SSE2 :PCMPEQW xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1286 SSE2 :PCMPEQD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1287 SSE2 :PCMPEQD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1290 SSE4.1 :PCMPEQQ xmm, xmm L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1291 SSE4.1 :PCMPEQQ xmm1, xmm2 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1294 SSE2 :PCMPGTB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1295 SSE2 :PCMPGTB xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1298 SSE2 :PCMPGTW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1299 SSE2 :PCMPGTW xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1302 SSE2 :PCMPGTD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1303 SSE2 :PCMPGTD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1306 SSE4.2 :PCMPGTQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1307 SSE4.2 :PCMPGTQ xmm1, xmm2 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1310 SSE2 :PAND xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1311 SSE2 :PAND xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1314 SSE2 :PANDN xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1315 SSE2 :PANDN xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1318 SSE2 :POR xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1319 SSE2 :POR xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1322 SSE2 :PXOR xmm, xmm L: 0.25ns= 0.5c T: 0.25ns= 0.50c 1323 SSE2 :PXOR xmm1, xmm2 L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1326 SSE2 :PMULHW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1328 SSE2 :PMULHUW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1330 SSSE3 :PMULHRSW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1332 SSE2 :PMULLW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1334 SSE4.1 :PMULLD xmm, xmm L: 5.50ns= 11.0c T: 5.50ns= 11.00c 1336 SSE4.1 :PMULDQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1338 SSE2 :PMULUDQ xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1340 SSSE3 :PMADDUBSW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1342 SSE2 :PMADDWD xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1344 SSE2 :PSLLW xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1346 SSE2 :PSLLW xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1348 SSE2 :PSLLD xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1350 SSE2 :PSLLD xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1352 SSE2 :PSLLQ xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1354 SSE2 :PSLLQ xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1356 SSE2 :PSLLDQ xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1358 SSE2 :PSRAW xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1360 SSE2 :PSRAW xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1362 SSE2 :PSRAD xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1364 SSE2 :PSRAD xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1366 SSE2 :PSRLW xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1368 SSE2 :PSRLW xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1370 SSE2 :PSRLD xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1372 SSE2 :PSRLD xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1374 SSE2 :PSRLQ xmm, xmm L: 1.00ns= 2.0c T: 1.00ns= 2.00c 1376 SSE2 :PSRLQ xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1378 SSE2 :PSRLDQ xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1380 SSE2 :PUNPCKHBW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1382 SSE2 :PUNPCKHWD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1384 SSE2 :PUNPCKHDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1386 SSE2 :PUNPCKHQDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1388 SSE2 :PUNPCKLBW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1390 SSE2 :PUNPCKLWD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1392 SSE2 :PUNPCKLDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1394 SSE2 :PUNPCKLQDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1396 SSE2 :PACKSSWB xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1398 SSE2 :PACKUSWB xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1400 SSE2 :PACKSSDW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1402 SSE4.1 :PACKUSDW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1404 SSE2 :PAVGB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1406 SSE2 :PAVGW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1408 SSE4.1 :PEXTRB r32, xmm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 1409 SSE4.1 :PINSRB xmm, r32, im8 L: [diff. reg. set] T: 0.50ns= 1.00c 1410 SSE4.1 :PEXTRB + PINSRB r32 L: 4.00ns= 8.0c T: 4.00ns= 8.00c 1414 SSE4.1 :PEXTRB r64, xmm, im8 L: [diff. reg. set] T: 3.50ns= 7.00c 1415 SSE4.1 :PEXTRB r64 + PINSRB r32 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 1418 SSE2 :PEXTRW r32, xmm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 1419 SSE2 :PINSRW xmm, r32, im8 L: [diff. reg. set] T: 0.50ns= 1.00c 1420 SSE2 :PEXTRW + PINSRW r32 L: 4.00ns= 8.0c T: 4.00ns= 8.00c 1424 AMD64 :PEXTRW r64, xmm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 1425 AMD64 :PEXTRW r64 + PINSRW r32 L: 4.00ns= 8.0c T: 4.00ns= 8.00c 1428 SSE4.1 :PEXTRD r32, xmm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 1429 SSE4.1 :PINSRD xmm, r32, im8 L: [diff. reg. set] T: 0.50ns= 1.00c 1430 SSE4.1 :PEXTRD + PINSRD r32 L: 4.00ns= 8.0c T: 4.00ns= 8.00c 1434 SSE4.1 :PEXTRQ r64, xmm, im8 L: [diff. reg. set] T: 3.50ns= 7.00c 1435 SSE4.1 :PINSRQ xmm, r64, im8 L: [diff. reg. set] T: 3.00ns= 6.00c 1436 SSE4.1 :PEXTRD + PINSRD r64 L: 6.50ns= 13.0c T: 6.50ns= 13.00c 1440 SSE4.1 :EXTRACTPS r32, xmm, im8 L: [diff. reg. set] T: 2.00ns= 4.00c 1442 SSE4.1 :EXTRACTPS r64, xmm, im8 L: [diff. reg. set] T: 3.50ns= 7.00c 1444 SSE4.1 :INSERTPS xmm, xmm, im8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1450 SSE2 :PMAXUB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1452 SSE4.1 :PMAXSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1454 SSE4.1 :PMAXUW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1456 SSE2 :PMAXSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1458 SSE4.1 :PMAXUD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1460 SSE4.1 :PMAXSD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1462 SSE2 :PMINUB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1464 SSE4.1 :PMINSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1466 SSE4.1 :PMINUW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1468 SSE2 :PMINSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1470 SSE4.1 :PMINUD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1472 SSE4.1 :PMINSD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1474 SSE2 :PSADBW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1476 SSSE3 :PSHUFB xmm, xmm L: 2.50ns= 5.0c T: 2.50ns= 5.00c 1478 SSE2 :PSHUFLW xmm, xmm, im8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1480 SSE2 :PSHUFHW xmm, xmm, im8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1482 SSE2 :PSHUFD xmm, xmm, im8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1484 SSE3 :ADDSUBPS xmm, xmm L: 1.50ns= 3.0c T: 0.50ns= 1.00c 1486 SSE3 :ADDSUBPD xmm, xmm L: 2.00ns= 4.0c T: 1.00ns= 2.00c 1488 SSE3 :HADDPS xmm, xmm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 1490 SSE3 :HADDPD xmm, xmm L: 3.00ns= 6.0c T: 2.50ns= 5.00c 1492 SSE3 :HSUBPS xmm, xmm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 1494 SSE3 :HSUBPD xmm, xmm L: 3.00ns= 6.0c T: 2.50ns= 5.00c 1496 SSE3 :MOVSLDUP xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1498 SSE3 :MOVSHDUP xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1500 SSE3 :MOVDDUP xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1502 SSE3 :LDDQU xmm, [m128 + 4] L: [memory dep.] T: 0.50ns= 1.00c 1504 SSSE3 :PABSB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1506 SSSE3 :PABSW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1508 SSSE3 :PABSD xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1510 SSSE3 :PALIGNR xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1512 SSSE3 :PHADDW xmm, xmm L: 4.50ns= 9.0c T: 4.50ns= 9.00c 1514 SSSE3 :PHADDD xmm, xmm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 1516 SSSE3 :PHADDSW xmm, xmm L: 4.50ns= 9.0c T: 4.50ns= 9.00c 1518 SSSE3 :PHSUBW xmm, xmm L: 4.50ns= 9.0c T: 4.50ns= 9.00c 1520 SSSE3 :PHSUBD xmm, xmm L: 3.00ns= 6.0c T: 3.00ns= 6.00c 1522 SSSE3 :PHSUBSW xmm, xmm L: 4.50ns= 9.0c T: 4.50ns= 9.00c 1524 SSSE3 :PSIGNB xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1526 SSSE3 :PSIGNW xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1528 SSSE3 :PSIGND xmm, xmm L: 0.50ns= 1.0c T: 0.25ns= 0.50c 1530 SSE4.1 :BLENDPS xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1532 SSE4.1 :BLENDVPS xmm, xmm, L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1534 SSE4.1 :BLENDPD xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1536 SSE4.1 :BLENDVPD xmm, xmm, L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1538 SSE4.1 :PBLENDW xmm, xmm, imm8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1540 SSE4.1 :PBLENDVB xmm, xmm, L: 2.00ns= 4.0c T: 2.00ns= 4.00c 1542 SSE4.1 :DPPS xmm, xmm, imm8 L: 7.50ns= 15.0c T: 6.00ns= 12.00c 1544 SSE4.1 :DPPD xmm, xmm, imm8 L: 6.00ns= 12.0c T: 4.00ns= 8.00c 1546 SSE4.1 :MPSADBW xmm, xmm, imm8 L: 3.50ns= 7.0c T: 2.50ns= 5.00c 1548 SSE4.1 :PHMINPOSUW xmm, xmm L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1550 SSE4.1 :PMOVSXBW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1552 SSE4.1 :PMOVSXBD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1554 SSE4.1 :PMOVSXBQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1556 SSE4.1 :PMOVSXWD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1558 SSE4.1 :PMOVSXWQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1560 SSE4.1 :PMOVSXDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1562 SSE4.1 :PMOVZXBW xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1564 SSE4.1 :PMOVZXBD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1566 SSE4.1 :PMOVZXBQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1568 SSE4.1 :PMOVZXWD xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1570 SSE4.1 :PMOVZXWQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1572 SSE4.1 :PMOVZXDQ xmm, xmm L: 0.50ns= 1.0c T: 0.50ns= 1.00c 1574 SSE4.1 :PTEST xmm, xmm L: [no true dep.] T: 0.50ns= 1.00c 1578 SSE4.1 :ROUNDSS xmm, xmm, imm8 L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1580 SSE4.1 :ROUNDPS xmm, xmm, imm8 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1582 SSE4.1 :ROUNDSD xmm, xmm, imm8 L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1584 SSE4.1 :ROUNDPD xmm, xmm, imm8 L: 2.50ns= 5.0c T: 1.00ns= 2.00c 1587 SSE4.2 :PCMPESTRI xmm, xmm, imm8 L: 10.50ns= 21.0c T: 10.50ns= 21.00c 1589 SSE4.2 :PCMPESTRM xmm, xmm, imm8 L: 8.50ns= 17.0c T: 8.50ns= 17.00c 1591 SSE4.2 :PCMPISTRI xmm, xmm, imm8 L: 8.50ns= 17.0c T: 8.50ns= 17.00c 1593 SSE4.2 :PCMPISTRM xmm, xmm, imm8 L: 6.50ns= 13.0c T: 6.50ns= 13.00c 1595 CLMUL :PCLMULQDQ xmm, xmm, imm8 L: 5.50ns= 11.0c T: 5.00ns= 10.00c 1971 RDRAND :RDRAND r16 L: [no true dep.] T: 577.15ns=1154.25c 1972 RDRAND :RDRAND r32 L: [no true dep.] T: 577.23ns=1154.42c 1973 RDRAND :RDRAND r64 L: [no true dep.] T: 577.23ns=1154.42c 1974 X86 :MOV+ADD r8, r8 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1975 X86 :MOV+ADD r16, r16 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1976 X86 :MOV+ADD r32, r32 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1977 AMD64 :MOV+ADD r64, r64 L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1978 MMX :MOVQ+PADDB mm, mm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1979 MMX :MOVQ+PADDW mm, mm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1980 MMX :MOVQ+PADDD mm, mm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1981 SSE2 :MOVQ+PADDQ mm, mm L: 3.50ns= 7.0c T: 3.50ns= 7.00c 1983 SSE :MOVSS+ADDSS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1985 SSE :MOVAPS+ADDPS xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1987 SSE2 :MOVSD+ADDSD xmm, xmm L: 2.00ns= 4.0c T: 0.50ns= 1.00c 1989 SSE2 :MOVAPD+ADDPD xmm, xmm L: 2.50ns= 5.0c T: 0.96ns= 1.92c 1991 SSE2 :MOVDQA+PADDB xmm, xmm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1992 SSE2 :MOVDQA+PADDW xmm, xmm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1993 SSE2 :MOVDQA+PADDD xmm, xmm L: 1.00ns= 2.0c T: 0.50ns= 1.00c 1994 SSE2 :MOVDQA+PADDQ xmm, xmm L: 3.50ns= 7.0c T: 3.50ns= 7.00c 2238 CLFLUSH :CLFLUSH [mem] L: [memory dep.] T: 57.38ns=114.75c 2248 X86 :MOV r1_8, r2_8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2249 X86 :MOV r1_16, r2_16 L: 0.50ns= 1.0c T: 0.30ns= 0.60c 2250 X86 :MOV r1_32, r2_32 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2251 AMD64 :MOV r1_64, r2_64 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2252 X86 :MOVSX r1_16, r2_8 L: 2.04ns= 4.1c T: 2.00ns= 4.00c 2253 X86 :MOVSX r1_32, r2_8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2254 AMD64 :MOVSX r1_64, r2_8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2255 X86 :MOVSX r1_32, r2_16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2256 AMD64 :MOVSX r1_64, r2_16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2257 AMD64 :MOVSXD r1_64, r2_32 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2258 X86 :MOVZX r1_16, r2_8 L: 2.04ns= 4.1c T: 2.00ns= 4.00c 2259 X86 :MOVZX r1_32, r2_8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2260 AMD64 :MOVZX r1_64, r2_8 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2261 X86 :MOVZX r1_32, r2_16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2262 AMD64 :MOVZX r1_64, r2_16 L: 0.50ns= 1.0c T: 0.50ns= 1.00c 2263 MMX :MOVQ mm1, mm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2264 SSE :MOVSS xmm1, xmm2 L: 0.50ns= 1.0c T: 0.46ns= 0.92c 2266 SSE :MOVAPS xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2268 SSE :MOVUPS xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2270 SSE2 :MOVSD xmm1, xmm2 L: 0.50ns= 1.0c T: 0.46ns= 0.92c 2272 SSE2 :MOVAPD xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2274 SSE2 :MOVUPD xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2276 SSE2 :MOVDQA xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2278 SSE2 :MOVDQU xmm1, xmm2 L: 0.25ns= 0.5c T: 0.25ns= 0.50c 2290 SSE :4xADDPS xm1,xm1 4x xm2,xm2 L: 10.00ns= 20.0c T: 10.00ns= 20.00c 2291 SSE :4xMULPS xm1,xm1 4x xm2,xm2 L: 17.00ns= 34.0c T: 17.00ns= 34.00c 2292 SSE2 :4xADDPD xm1,xm1 4x xm2,xm2 L: 14.00ns= 28.0c T: 14.00ns= 28.00c 2293 SSE2 :4xMULPD xm1,xm1 4x xm2,xm2 L: 25.00ns= 50.0c T: 25.00ns= 50.00c 2294 LNOP :LNOP3 [eax], eax L: [no true dep.] T: 0.25ns= 0.50c 2295 LNOP :LNOP4 [eax+disp8], eax L: [no true dep.] T: 0.25ns= 0.50c 2296 LNOP :LNOP5 [SIB+disp8], eax L: [no true dep.] T: 0.25ns= 0.50c 2297 LNOP :LNOP6 [SIB+disp8], ax L: [no true dep.] T: 0.25ns= 0.50c 2298 LNOP :LNOP7 [eax+disp32], eax L: [no true dep.] T: 0.25ns= 0.50c 2299 LNOP :LNOP8 [SIB+disp32], eax L: [no true dep.] T: 0.26ns= 0.51c 2300 LNOP :LNOP9 [SIB+disp32], ax L: [no true dep.] T: 0.50ns= 1.00c 2301 LNOP :2x66 LNOPA [SIB+disp32], ax L: [no true dep.] T: 0.50ns= 1.00c 2302 LNOP :3x66 LNOPB [SIB+disp32], ax L: [no true dep.] T: 2.00ns= 4.00c 2303 LNOP :4x66 LNOPC [SIB+disp32], ax L: [no true dep.] T: 2.00ns= 4.00c 2304 LNOP :5x66 LNOPD [SIB+disp32], ax L: [no true dep.] T: 2.00ns= 4.00c 2305 LNOP :6x66 LNOPE [SIB+disp32], ax L: [no true dep.] T: 3.50ns= 7.00c 2306 LNOP :7x66 LNOPF [SIB+disp32], ax L: [no true dep.] T: 3.50ns= 7.00c 4354 X86 :SHLD r1_16, r2_16, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4355 X86 :SHLD r1_32, r2_32, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4356 AMD64 :SHLD r1_64, r2_64, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4357 X86 :SHLD r1_16, r2_16, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4358 X86 :SHLD r1_32, r2_32, cl L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4359 AMD64 :SHLD r1_64, r2_64, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4360 X86 :SHRD r1_16, r2_16, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4361 X86 :SHRD r1_32, r2_32, imm8 L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4362 AMD64 :SHRD r1_64, r2_64, imm8 L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4363 X86 :SHRD r1_16, r2_16, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4364 X86 :SHRD r1_32, r2_32, cl L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4365 AMD64 :SHRD r1_64, r2_64, cl L: 5.00ns= 10.0c T: 5.00ns= 10.00c 4366 X86 :ADC r8, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4367 X86 :ADC r16, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4368 X86 :ADC r32, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4369 AMD64 :ADC r64, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4370 X86 :ADC r16, imm16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4371 X86 :ADC r32, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4372 AMD64 :ADC r64, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4373 X86 :ADC al, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4374 X86 :ADC ax, imm16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4375 X86 :ADC eax, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4376 AMD64 :ADC rax, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4377 X86 :ADC r8, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4378 X86 :ADC r16, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4379 X86 :ADC r32, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4380 AMD64 :ADC r64, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4381 X86 :ADC r16, imm16_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4382 X86 :ADC r32, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4383 AMD64 :ADC r64, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4384 X86 :ADC al, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4385 X86 :ADC ax, imm16_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4386 X86 :ADC eax, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4387 AMD64 :ADC rax, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4388 X86 :SBB r8, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4389 X86 :SBB r16, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4390 X86 :SBB r32, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4391 AMD64 :SBB r64, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4392 X86 :SBB r16, imm16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4393 X86 :SBB r32, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4394 AMD64 :SBB r64, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4395 X86 :SBB al, imm8 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4396 X86 :SBB ax, imm16 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4397 X86 :SBB eax, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4398 AMD64 :SBB rax, imm32 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4399 X86 :SBB r8, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4400 X86 :SBB r16, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4401 X86 :SBB r32, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4402 AMD64 :SBB r64, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4403 X86 :SBB r16, imm16_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4404 X86 :SBB r32, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4405 AMD64 :SBB r64, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4406 X86 :SBB al, imm8_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4407 X86 :SBB ax, imm16_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4408 X86 :SBB eax, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4409 AMD64 :SBB rax, imm32_0 L: 1.00ns= 2.0c T: 1.00ns= 2.00c 4410 AMD64 :LEA r16, [disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4411 AMD64 :LEA r32, [disp32] L: 0.25ns= 0.5c T: 0.25ns= 0.50c 4412 AMD64 :LEA r64, [disp32] L: 0.25ns= 0.5c T: 0.25ns= 0.50c 4413 AMD64 :LEA r16, [r64] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4414 AMD64 :LEA r32, [r64] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4415 AMD64 :LEA r64, [r64] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4416 AMD64 :LEA r16, [r64 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4417 AMD64 :LEA r32, [r64 + disp8] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4418 AMD64 :LEA r64, [r64 + disp8] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4419 AMD64 :LEA r16, [r64 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4420 AMD64 :LEA r32, [r64 + disp32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4421 AMD64 :LEA r64, [r64 + disp32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4422 AMD64 :LEA r16, [r64 + r64] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4423 AMD64 :LEA r32, [r64 + r64] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4424 AMD64 :LEA r64, [r64 + r64] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4425 AMD64 :LEA r16, [r64 + r64 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4426 AMD64 :LEA r32, [r64 + r64 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4427 AMD64 :LEA r64, [r64 + r64 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4428 AMD64 :LEA r16, [r64 + r64 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4429 AMD64 :LEA r32, [r64 + r64 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4430 AMD64 :LEA r64, [r64 + r64 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4431 AMD64 :LEA r16, [r64 + r64 * 8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4432 AMD64 :LEA r32, [r64 + r64 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4433 AMD64 :LEA r64, [r64 + r64 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4434 AMD64 :LEA r16, [r64 + r64 * 8 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4435 AMD64 :LEA r32, [r64 + r64 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4436 AMD64 :LEA r64, [r64 + r64 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4437 AMD64 :LEA r16, [r64 + r64 * 8 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4438 AMD64 :LEA r32, [r64 + r64 * 8 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4439 AMD64 :LEA r64, [r64 + r64 * 8 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4440 AMD64 :ASP LEA r16, [disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4441 AMD64 :ASP LEA r32, [disp32] L: 0.25ns= 0.5c T: 0.25ns= 0.50c 4442 AMD64 :ASP LEA r64, [disp32] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4443 AMD64 :ASP LEA r16, [r32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4444 AMD64 :ASP LEA r32, [r32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4445 AMD64 :ASP LEA r64, [r32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4446 AMD64 :ASP LEA r16, [r32 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4447 AMD64 :ASP LEA r32, [r32 + disp8] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4448 AMD64 :ASP LEA r64, [r32 + disp8] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4449 AMD64 :ASP LEA r16, [r32 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4450 AMD64 :ASP LEA r32, [r32 + disp32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4451 AMD64 :ASP LEA r64, [r32 + disp32] L: 0.50ns= 1.0c T: 0.25ns= 0.50c 4452 AMD64 :ASP LEA r16, [r32 + r32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4453 AMD64 :ASP LEA r32, [r32 + r32] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4454 AMD64 :ASP LEA r64, [r32 + r32] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4455 AMD64 :ASP LEA r16, [r32 + r32 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4456 AMD64 :ASP LEA r32, [r32 + r32 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4457 AMD64 :ASP LEA r64, [r32 + r32 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4458 AMD64 :ASP LEA r16, [r32 + r32 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4459 AMD64 :ASP LEA r32, [r32 + r32 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4460 AMD64 :ASP LEA r64, [r32 + r32 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4461 AMD64 :ASP LEA r16, [r32 + r32 * 8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4462 AMD64 :ASP LEA r32, [r32 + r32 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4463 AMD64 :ASP LEA r64, [r32 + r32 * 8] L: 0.50ns= 1.0c T: 0.50ns= 1.00c 4464 AMD64 :ASP LEA r16, [r32 + r32 * 8 + disp8] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4465 AMD64 :ASP LEA r32, [r32 + r32 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4466 AMD64 :ASP LEA r64, [r32 + r32 * 8 + disp8] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4467 AMD64 :ASP LEA r16, [r32 + r32 * 8 + disp32] L: 2.00ns= 4.0c T: 2.00ns= 4.00c 4468 AMD64 :ASP LEA r32, [r32 + r32 * 8 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c 4469 AMD64 :ASP LEA r64, [r32 + r32 * 8 + disp32] L: 1.00ns= 2.0c T: 0.50ns= 1.00c