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Bus Overclocking: Memory

The memory subsystem is often the first to lose stability during front-side bus overclocking. The quality of the memory itself is important in determining overclocking potential. Generic memory types should be avoided, as the memory chip manufacturer often has no control over the production processes used in building generic components. Small manufacturers purchase memory chips from brand-name corporations and mount them on low-quality printed circuit boards. These boards often fail quality testing at overclocked speeds because they are designed to meet minimum quality standards.

Quality memory modules undergo production and testing within the same manufacturing environment. Large manufacturers, such as Micron's Crucial Technology retail sales division, offer superior quality testing. Each Crucial memory module must meet the same stringent standards as Micron's OEM modules. This high degree of vigilance usually produces an excellent chip.

Some vendors take advantage of the confusion surrounding memory quality. For example, Micron provides memory chips for sale to other manufacturers for assembly on a generic printed circuit board. Some vendors receive the generic memory, then attempt to sell it as a brand-name product because each individual chip is tagged with Micron's manufacturing and model codes. Users expect a quality product, but instead they receive a generic part that may not meet Micron quality assurance standards. Purchasing memory directly from large-scale manufacturers is the best way to avoid low-quality components though some smaller manufacturers do have good testing procedures and warranties.

Type and performance ratings are the two most important things to consider when evaluating whether or not a memory module is suitable for an overclocked configuration. Better-quality PC-133 SDRAM and PC-2100 DDR memory modules can operate up to 33 MHz beyond their factory ratings with good stability. The high-frequency RAMBUS designs can often go 100 MHz beyond their rated speed. Older fast-page and extended data-out technologies are not as scalable, with overclocking potential less than 33 MHz. As with processors, the maximum overclocked speed depends on a number of design, production, and testing factors.

You may need to tweak memory timing values when overclocking the memory bus. Most motherboards allow memory timing rates to be defined in the BIOS Setup interface. While you must use trial and error to determine the best timing pattern, setting CAS (column address strobe) latency can be a valuable overclocking tool. CAS latency determines the rate for memory read, write, and move operations.

Most quality memory will feature a CAS latency of 2 for SDRAM, or up to 2.5 for DDR memory modules. Adjusting this value to 3 will often enable memory modules that would otherwise fail at overclocked bus rates to operate without any problems. As latency increases, bandwidth decreases. However, performance loss is negligible because subsequent overclocking of the memory bus can deliver more available bandwidth to offset latency. Benchmark testing is required to determine the proper relationships among timing, latency, and operating frequencies.

Many motherboards, especially those featuring non-Intel chipsets, give users the ability to specify custom bus rates correlated to the front-side bus. This can prove invaluable when overclocking the front-side bus. Most chipsets feature a fixed multiplier range for PCI, AGP, and other interconnect bus operations, but many chipsets skew the memory bus rate through an additive or subtractive process. The skew value is often derived from the rate of the PCI bus, which is 33 MHz at default clock operation.

Manipulating the memory bus is an important aspect of overclocking. Let's look at the Intel Pentium III e series, for example. This processor operates with a 100-MHz front-side bus. Many non-Intel motherboards allow the memory bus to be offset from the front-side bus by 33 MHz. Thus, a high-performance PC-133 SDRAM in asynchronous mode can replace the original synchronous default. The P3e processor can be overclocked to a front-side bus rate of 133 MHz. If the user already has PC-133 memory, the memory bus can be configured for synchronous operation. However, with low-quality PC-100 memory, the user could opt to use an asynchronous 100 MHz memory bus (133 MHz minus 33 MHz), thus improving stability while allowing the processor to be overclocked to the 133-MHz front-side rate.

The P3e system is only one example. Most chipsets support the skewing of memory bus rates, not only for overclocking but also to improve performance in other ways. In the P3e with PC-100 SDRAM example, assume a user wants to upgrade to PC-166 technology. After changing out the old memory, he or she can use the additive asynchronous mode to maximize memory bandwidth. This process allows the front-side bus to retain its 133-MHz overclocked rate, while the memory bus is skewed to achieve 166 MHz.

Sadly, most Intel chipsets do not allow skewing the memory bus though asynchronous operation, though nearly all non-Intel chipsets do. Remember that lowering operating speeds for system buses, especially the memory bus, may also reduce performance, even when the processor or front-side bus is overclocked.


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