PLL Circuit

A phased locked loop or PLL circuit resides at the simplest level of the frequency generation equation. Some older designs were based around a set frequency crystal, though PLL circuits have been the mainstay logic timing control technology for many years now. The PLL acts as a base frequency synthesizer by cycling its generated signal according to a preprogrammed routine. The locking of the circuit in a specific pattern creates a phase shift in the signal, thus producing a cycling effect that drives the frequency generation scheme. The PLL signal travels across a motherboard bus, dedicated to timing, to dictate the frequency needed for the operation of other buses. The primary recipient of the PLL signal is the motherboard's main controller, known as the chipset.

Chipset designs differ greatly across the wide range of platforms available, though the basic concept is shared. The frequency rate at which the chipset operates is the motherboard's primary operating speed. The chipset provides a communications hub for all of the system's various components. It also controls routing and logic for most primary control operations, ranging from memory addressing to data transfers across different bus standards.

The term front-side bus rate is widely used to describe the motherboard's frequency rate, as this same rate is often also used for the memory and processor buses within a traditional system design. To confuse matters, many of the latest architectures like the AMD Athlon or Intel Pentium 4 blur the relationships among each of these three primary buses by separating each bus at the chipset connection point. The back-side bus, on the other hand, is generally composed of additional input/output mechanisms, such as PCI and AGP connection buses.

Upon receiving the base PLL signal, the chipset generates a signal to the other buses. The most important signal to overclockers is the processor bus rate of the front-side bus, as this directly determines the central processing unit's core operating speed when combined with the processor multiplier value. The PLL circuit provides the base timing signal for the motherboard chipset, which in turn passes the value to the processor. The processor then internally multiplies this clock rate to derive its core clock operating frequency.

Frequency Timing Scheme

The best way to describe this process is to refer to a common system design, such as the Pentium III platform. A quick examination of a common chipset, such as the VIA's Pro133A model, shows how the process actually works. The Pro133A chipset is built primarily for a 100-MHz operation, though the Pentium III processor itself features a much higher operating speed. The core processor rate is determined by inserting a multiplier into the timing signal. Thus, a Pentium III 650e processor uses a 6.5x clock multiplier, given that the chipset is operating at 100 MHz. Multiplier values are generally spaced in .5x increments; this scheme allows for a wide range of operating frequencies when speed-binning processors.

Most platforms use the timing scheme presented in the Pentium III example, though some of the newer architectures, notably AMD's Athlon and Intel's Pentium 4, can alter the interpretation. The x86 Athlon uses a modified bus architecture developed from a non-x86 DEC Alpha EV6. The Athlon inserts a double data rate (DDR) signaling pattern into the processor-to-chipset interconnect bus. DDR signaling uses the rising and falling edges of the base clock signal to effectively transfer twice as much data as traditional buses can transfer in a similar period of time.

The Pentium 4 goes one step further with a pseudo quad data rate (QDR) processor bus design. Without going deeply into deeply technical issues, the P4 processor bus can be viewed as implementing DDR signaling across two 180-degree co-phased timing signals that travel essentially the same bus pathway. More about each of these platforms can be found in the architecture-specific overclocking sections of this book.

The Pentium 4 goes one step further with a pseudo quad data rate (QDR) processor bus design. Without going deeply into deeply technical issues, the P4 processor bus can be viewed as implementing DDR signaling across two 180degree co-phased timing signals that travel essentially the same bus pathway. More about each of these platforms can be found in the architecture-specific overclocking sections of this book.

A software application called CPUID can help you determine the particular model and speed grade of your PC processor if you are unsure of its configuration. CPU-Z by Frank Delatree is a popular freeware example. This valuable utility can be obtained at http://www.cpuid.com/cpuz.htm. CPU-Z can provide information about multiplier values, bus rates, and various other technological aspects of most currently available processors.